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| User's Manual PD77016 Family Digital Signal Processor Instructions PD77015 PD77016 PD77017 PD77018 PD77018A PD77019 PD77110 PD77111 PD77112 PD77113 PD77114 Document No. U13116EJ2V0UM00 (2nd edition) Date Published July 2000 N CP(K) (c) Printed in Japan 1998 [MEMO] 2 User's Manual U13116EJ2V0UM00 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after poweron for devices having reset function. User's Manual U13116EJ2V0UM00 3 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: The customer must judge the the need for licence: PD77016, PD77019-013, PD77110 PD77015, PD77017, PD77018, PD77018A, PD77019, PD77111, PD77112, PD77113, PD77114 * The information in this document is current as of February, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 4 User's Manual U13116EJ2V0UM00 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 User's Manual U13116EJ2V0UM00 5 Major Revisions in This Edition Page Throughout p. 78 Description Addition of mPD77110, 77111, 77112, 77113, and 77114 as target devices 3.4 Load/Store Instructions Addition of description to Caution 1 of LSPA (parallel load/store instruction) 3.4 Load/Store Instructions Addition of description to Caution 1 of LSSE (section load/store instruction) 3.8 Hardware Loop Instructions Addition of Caution 2 of REP (repeat instruction) 3.8 Hardware Loop Instructions Addition of Caution 2 and change of Caution 3 of LOOP (loop instruction) 3.9 Control Instructions Change of description and addition of Caution 3 of STOP (stop instruction) p. 84 p. 109 p. 111 p. 113 The mark shows major revised points. 6 User's Manual U13116EJ2V0UM00 INTRODUCTION Target Readers: This manual is intended for users who wish to understand the functions of the PD77016 Family devices and to design and develop software/hardware application systems using these micocontrollers. Purpose: This manual is intended to give users an understanding of the instruction functions provided in PD77016 Family devices, and is designed to be used as a reference manual when developing software or hardware application systems using these microcontrollers. Organization: This manual consists of the following sections: * CHAPTER 1 * CHAPTER 2 OUTLINE INSTRUCTION CATEGORIES AND INSTRUCTION FUNCTIONS * CHAPTER 3 EXPLANATION OF INSTRUCTIONS * APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS * APPENDIX B INSTRUCTION SETS * APPENDIX C INDEX How to Use This Manual: It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcomputers. The PD77016 Family represents PD7701x Family devices (PD77016, 77015, 77017, 77018, 77018A, and 77019) and PD77111 Family (PD77110, 77111, 77112, 77113, and 77114). Unless there are differences in function or operation, read the PD77016 Family as the corresponding products. If there are differences among family products, they are described under their respective names. Legends: Data significance: Note: Caution: Remarks: Bold text: Higher digits on the left and lower on the right Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Important items Numerical representation: Binary ... 0bXXXX Decimal ... XXXX { }: Hexadecimal ... 0xXXXX Either of the items enclosed within { selected. } can be User's Manual U13116EJ2V0UM00 7 Related Documents: The related documents listed below may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Pamphlet Product name Data Sheet Architecture U12395E U10891E U10902E U10503E Instructions This document Basic software U11958E User's Manual Application Note PD77016 PD77015 PD77017 PD77018 PD77018A PD77019 PD77019-013 PD77110 PD77111 PD77112 PD77113 PD77114 U11849E U13053E U12801E U14623E U14373E Documents Related to Development Tools Document Name IE-77016-98, IE-77016-PC User's Manual IE-11016-CM-LC User's Manual RX77016 User's Manual Function Configuration Tool RX77016 Application Note HOST API Hardware Document No. U13044E U14139E U14397E U14404E U14371E Caution The documents listed above are subject to change without notice. Be sure to use the latest documents when designing. 8 User's Manual U13116EJ2V0UM00 CONTENTS CHAPTER 1 OUTLINE ............................................................................................................................ 13 1.1 Assembly Description ............................................................................................................. 13 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 Coding instructions ........................................................................................................................ 13 Parallel coding ............................................................................................................................... 13 Coding trinomial operations ........................................................................................................... 14 Pointer operations ......................................................................................................................... 14 Coding conditional instructions ...................................................................................................... 14 Coding hardware loop instructions ................................................................................................ 14 Symbols and corresponding registers ........................................................................................... 16 General-purpose register partition format ..................................................................................... 17 Data pointer modification ............................................................................................................... 18 1.2 Conventions Used for Instruction Descriptions ................................................................... 16 1.2.1 1.2.2 1.2.3 1.3 Description Format .................................................................................................................. 19 CHAPTER 2 INSTRUCTION CATEGORIES AND INSTRUCTION FUNCTIONS .............................. 21 2.1 Classification by Instruction Word ........................................................................................ 21 2.1.1 2.1.2 Classification by instruction word format (category classification) ................................................ 21 Classification by instruction function (functional classification) ..................................................... 21 CHAPTER 3 EXPLANATION OF INSTRUCTIONS .............................................................................. 23 3.1 Trinomial Operation Instructions ........................................................................................... 23 3.2 Binomial Operation Instructions ............................................................................................ 36 3.3 Monomial Operation Instructions .......................................................................................... 57 3.4 Load/Store Instructions .......................................................................................................... 74 3.5 Inter-Register Transfer Instructions ...................................................................................... 93 3.6 Immediate Value Set Instruction ............................................................................................ 96 3.7 Branch Instructions ................................................................................................................. 99 3.8 Hardware Loop Instructions ................................................................................................. 107 3.9 Control Instructions .............................................................................................................. 114 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS ......................................................... A.1 Three-Operand Instructions ................................................................................................. A.2 Two-Operand Instructions .................................................................................................... A.3 Immediate Value Operation Instructions ............................................................................. A.4 Load/Store Instructions ........................................................................................................ A.5 Inter-Register Transfer Instruction ...................................................................................... A.6 Immediate Value Set Instruction .......................................................................................... A.7 Branch Instructions ............................................................................................................... A.8 Hardware Loop Instructions ................................................................................................. A.9 CPU Control Instructions ...................................................................................................... A.10 Conditional Instructions ....................................................................................................... 120 121 123 125 126 129 130 131 133 135 136 User's Manual U13116EJ2V0UM00 9 APPENDIX B INSTRUCTION SETS .................................................................................................... 138 APPENDIX C INDEX ............................................................................................................................. 144 10 User's Manual U13116EJ2V0UM00 LIST OF FIGURES Figure No. 1-1 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 Title Page Partition Formats of General-Purpose Registers ............................................................................ 17 Three-Operand Instruction Format ................................................................................................. 122 Two-Operand Instruction Format .................................................................................................... 124 Immediate Value Operation Instruction Format ............................................................................. 125 Load/Store Instruction Format ........................................................................................................ 127 Inter-Register Transfer Instruction Format ..................................................................................... 129 Immediate Value Set Instruction Format ....................................................................................... 130 Branch Instruction Format .............................................................................................................. 132 Hardware Loop Instruction Format ................................................................................................ 134 CPU Control Instruction Format ..................................................................................................... 135 Conditional Instruction Format ....................................................................................................... 137 User's Manual U13116EJ2V0UM00 11 LIST OF TABLES Table No. 1-1 1-2 A-1 Title Page Symbols and Corresponding Registers ........................................................................................... 16 Data Pointer Modify .......................................................................................................................... 18 Formats of Instruction Words ......................................................................................................... 120 12 User's Manual U13116EJ2V0UM00 CHAPTER 1 OUTLINE An instruction word in the PD77016 Family is composed of 32 bits. Each instruction word is partitioned logically, allowing plural functional instructions to be included in a single instruction word. All operation instructions and transfer instructions are executed in one instruction cycle, while loop instructions and branch instructions are executed in two or three instruction cycles. The PD77016 has the following assembly instruction features. * 32-bit instruction words * Nine instruction function groups * Plural instructions can be described in one instruction word. * Flexible description of conditional operations by combining independent conditional instructions 1.1 Assembly Description 1 1.1.1 Coding instructions The assembly language for the PD77016 Family uses arithmetic symbols such as +, -, *, /, and =, instead of general mnemonics such as ADD and MOV, for improved program readability. This assembly language requires a semicolon ";" to indicate the end of each line in the same manner as the C language. Note that this assembler treats all codes as one line until a semicolon, even though one instruction description may fill several lines. A description example is provided below: 2 3 Description example: * R1 = R0; ........................ Assigns the R0 register contents to the R1 register. * R5 = *DP0; .................... Assigns the X memory contents to the R5 register by using the DP0 register as a pointer. * R4 = R2 + R3; ............... Adds the R2 and R3 register contents, and assigns the result to the R4 register. 1.1.2 Parallel coding To describe parallel operations of the PD77016 Family, up to three instructions can be described in parallel: an operation instruction (trinomial, binomial, monomial operation instructions) and two transfer instructions for data movements via X and Y buses. Description example: R1 = R0 R2 = *DP0 *DP4 = R3H; .......... Assigns the R0 register contents to the R1 register, then assigns the X memory contents to the R2 register using the DP0 register as a pointer, and assigns the R3H register contents to the Y memory using the DP4 register as a pointer. Remark In the example above, the PD77016 Family first executes the operational instruction, then executes the transfer instructions. 4 5 6 A B C User's Manual U13116EJ2V0UM00 13 CHAPTER 1 OUTLINE 1.1.3 Coding trinomial operations The PD77016 Family supports trinomial instructions that use three operands to describe the operation of the incorporated multiplier (the result obtained from multiplication by hardware is added to another register). Description example: R0 = R0 + R1L * R2L; .......... Multiplies the R1L register and the R2L register contents, then adds the result to the R0 register contents, and stores the sum in the R0 register. 1.1.4 Pointer operations The PD77016 Family is provided with instructions that add and subtract the pointer value after executing the transfer instructions explained in 1.1.2 and 1.1.3 above. For details on pointer operations, refer to PD7701x Family User's Manual Architecture or PD77111 Family User's Manual Architecture. Description example: R1 = *DP0++ R2 = *DP4##; .......... Executes transfer instructions using the DP0 and DP4 registers as pointers, adds 1 to the DP0 contents, and adds the DN4 (supplement register) value to the DP4 contents. 1.1.5 Coding conditional instructions The PD77016 Family is provided with conditional instructions that can use a register value as the condition. These instructions are executed only when the register value matches the specified condition. By using these instructions, the number of branch (conditional) instructions required in conditional operation can be reduced. For details on the conditional instructions, refer to section 3.9 Conditional instruction of control instruction (COND). Description example: if (R0 < 0) R1L + = R2L; .......... Adds the R2 register contents to the R1 register contents when the R0 register value is negative. 1.1.6 Coding hardware loop instructions The PD77016 Family is provided with hardware loop instructions, which enable instructions consisting of 1 to 255 lines to be repeatedly executed 1 to 32767 times. To describe this operation, either the REPEAT or LOOP instruction is used depending on the number of repeated instruction lines. Nesting of loops is allowed (up to four levels). 14 User's Manual U13116EJ2V0UM00 CHAPTER 1 OUTLINE Description example: * To execute one line of instruction two or more times: REPEAT 32 R0 = R0 + R1L * R2L R1 = *DP0++ R2 = *DP4++; * To execute 2 to 255 lines of instructions two or more times: LOOP R1L { R0 = R0 + R1L * R2L; * * * R4 = R4 - 1; }; * To execute a loop within a loop function (nesting of loops): LOOP 64 { R0 = R0 + R1L * R2L; * * * LOOP R1L { R3 = R0 + R4; * * * }; R4 = R4 - 1; R5 = R5 + 1; NOP; }; User's Manual U13116EJ2V0UM00 15 CHAPTER 1 OUTLINE 1.2 Conventions Used for Instruction Descriptions 1.2.1 Symbols and corresponding registers In the following sections, registers are described in a generalized style using symbols. The relationship between the symbols and the corresponding registers is shown in Table 1-1. Table 1-1. Symbols and Corresponding Registers Symbols ro, ro' ro'' rl, rl' rh, rh' re reh dp dn dm dpx dpy dpx_mod dpy_mod dp_imm * xxx R0 to R7 R0L to R7L R0H to R7H R0E to R7E R0EH to R7EH DP0 to DP7 DN0 to DN7 DMX and DMY DP0 to DP3 DP4 to DP7 Corresponding Registers DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 0 to 3) DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 4 to 7) DPn##imm (n = 0 to 7) Memory contents with address xxx Example * DP0 indicates the contents of address 1000 when the contents of the DP0 register is 1000. 16 User's Manual U13116EJ2V0UM00 CHAPTER 1 OUTLINE 1.2.2 General-purpose register partition format General-purpose registers can be partially accessed when an operation or transfer is executed. The partial access methods are classified into the five formats shown in Figure 1-1. Figure 1-1. Partition Formats of General-Purpose Registers 39 R0 to R7 D 0 39 R0EH to R7EH D 16 15 X 0 39 R0E to R7E D 32 31 X 0 39 R0H to R7H X 32 31 D 16 15 X 0 39 R0L to R7L Remark D: Numeral X: Invalid X 16 15 D 0 User's Manual U13116EJ2V0UM00 17 CHAPTER 1 OUTLINE 1.2.3 Data pointer modification If indirect addressing using a pointer (DPn) is executed, the data pointer is, in most cases, modified after memory access. Table 1-2 shows the relationship between the descriptions of data pointer modify and the corresponding operations. Table 1-2. Data Pointer Modify Description DPn DPn++ DPn- - DPn## Operation No operation (The value of DPn is not changed.) DPn DPn + 1 DPn DPn - 1 DPn DPn + DNn (Adds DP0 through DP7 values to DN0 through DN7 values, respectively.) Example: DP0 DP0 + DN0 (n = 0 to 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH (n = 4 to 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH DPn%% !DPn## Accesses memory after bit reverse for DPn. After memory access, DPn DPn + DNn DPn DPn + imm DPn##imm 18 User's Manual U13116EJ2V0UM00 CHAPTER 1 OUTLINE 1.3 Description Format Instruction symbol Instruction type MADD Trinomial operation ro = ro + rh * rh' Name of instruction: Mnemonic: Example Explanation Multiply add ro = ro + rh * rh' R1 = R1 + R0H * R4H MADD Details on instruction operations are described. Operation target is marked with solid line. Instruction to add the product of 16-bit data x 16-bit data to 40-bit data. 39 ro S 39 rh 39 rh' 39 ro S 32 31 30 . + 32 31 30 S. x 32 31 30 S. = 32 31 30 . 16 15 0 16 15 0 16 15 0 16 15 0 Execution cycle 1 Number of instruction execution cycles Instructions marked with "Yes" can be described with this instruction. Parallel load/store Yes Inter-register transfer No Branch No Conditional No Instruction that can be described concurrently Trinomial No Caution Binomial No Monomial No Description that should be read carefully. User's Manual U13116EJ2V0UM00 19 [MEMO] 20 User's Manual U13116EJ2V0UM00 CHAPTER 2 INSTRUCTION CATEGORIES AND INSTRUCTION FUNCTIONS An instruction is composed of 32 bits which are partitioned into several fields to concurrently manage various resources in the device. Instructions can be classified into various formats according to the field partition methods. These formats are further classified by function group into several categories to facilitate the use of instructions. 2.1 Classification by Instruction Word This section describes two instruction classifications: category and functional classifications. 2.1.1 Classification by instruction word format (category classification) Instructions can be classified by the format in which the instruction words are partitioned into fields. Such classification is called category classification. Under this classification, categories are mutually exclusive. In other words, an instruction which is described in a particular format cannot be used in any other format. If the entire program is described according to this classification, the programmer can easily trace which functions are concurrently performed by a one-word instruction execution. This also allows users to create bit patterns of instruction words by synthesizing element fields, and to analyze concurrently performed functions based on the bit pattern of an instruction word. Although this classification is closely related to the architecture of language processors including assemblers, programmers do not necessarily have to be aware of these formats. The details of the category classification are provided in Appendix A. 2.1.2 Classification by instruction function (functional classification) Classifying instructions according to their functions is called functional classification. instructions are classified into the following nine functional groups: * Trinomial operation * Binomial operation * Monomial operation * Load/store * Inter-register transfer * Immediate value set * Branch * Hardware loop * Control Remark: The classification indicated in 2.1.2 above does not imply that each instruction is exclusive within one word; plural instructions may be concurrently described in the same instruction word. For details, refer to CHAPTER 3 EXPLANATION OF INSTRUCTIONS. This classification helps programmers understand overall instructions and is convenient when creating application programs. In this manual, User's Manual U13116EJ2V0UM00 21 [MEMO] 22 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS This section describes instructions of the PD77016 Family based on the functional classification. The following nine types of instructions are provided: 3.1 Trinomial Operation Instructions 3.2 Binomial Operation Instructions 3.3 Monomial Operation Instructions 3.4 Load/Store Instructions 3.5 Inter-Register Transfer Instruction 3.6 Immediate Value Set Instruction 3.7 Branch Instructions 3.8 Hardware Loop Instructions 3.9 Control Instructions 3.1 Trinomial Operation Instructions Instruction for specifying operations with the multiply-accumulator. Any three registers can be specified for the operands (inputs) from the general-purpose register file, and any one of the registers specified for the operands can be specified for the output destination. The following trinomial operation instructions are provided (symbol in parentheses is an abbreviation of each instruction). Multiply add Multiply sub Sign unsign multiply add 1-bit shift multiply add 16-bit shift multiply add (MADD) (MSUB) (SUMA) (MAS1) (MAS16) Unsign unsign multiply add (UUMA) User's Manual U13116EJ2V0UM00 23 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MADD Trinomial operation ro = ro + rh * rh' Name of instruction: Mnemonic: Example Explanation Multiply add ro = ro + rh * rh' R1 = R1 + R0H * R4H Instruction to add the product of 16-bit data x 16-bit data to 40-bit data. MADD The product of the value of bits 31 to 16 of the general-purpose register specified by rh multiplied by the value of bits 31 to 16 of the general-purpose register specified by rh' is added to the value of bits 39 to 0 of the general-purpose register specified by ro. The sum is stored in bits 39 to 0 of the general-purpose register specified by ro. The 16-bit values specified by rh and rh' and the 40bit value specified by ro are data formats represented with two's complement. 39 ro S 32 31 30 . + 39 rh 32 31 30 S. 16 15 0 16 15 0 x 39 rh' 32 31 30 S. = 39 ro S 32 31 30 . 16 15 0 16 15 0 On the assumption that a decimal point is located between bit 31 and bit 30 of the value of the general-purpose registers specified by rh and rh', the product to be added to the value of the general-purpose register specified by ro is a value with a decimal point located between bit 31 and bit 30, sign-extended to bits 39 to 32 and with bit 0 set to 0. 24 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MADD MADD Trinomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If the addition results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 25 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MSUB Trinomial operation ro = ro - rh * rh' Name of instruction: Mnemonic: Example Explanation Multiply sub ro = ro - rh * rh' R1 = R1 - R0H * R4H Instruction to subtract the product of 16-bit data x 16-bit data from 40-bit data. MSUB The product of bits 31 to 16 of register rh multiplied by bits 31 to 16 of register rh' is subtracted from bits 39 to 0 of register ro. The 16-bit values specified by rh and rh' and the 40-bit value specified by ro are data formats represented with two's complement. 39 ro S 32 31 30 . -- 39 rh 32 31 30 S. 16 15 0 16 15 0 x 39 rh' 32 31 30 S. = 39 ro S 32 31 30 . 16 15 0 16 15 0 On the assumption that a decimal point is located between bit 31 and bit 30 of the value of the general-purpose registers specified by rh and rh', the product to be added to the value of the general-purpose register specified by ro is a value with a decimal point located between bit 31 and bit 30, sign-extended to bits 39 to 32 and with bit 0 set to 0. 26 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MSUB MSUB Trinomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If the subtraction results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 27 CHAPTER 3 EXPLANATION OF INSTRUCTIONS SUMA Trinomial operation ro = ro + rh * rl Name of instruction: Mnemonic: Example Explanation Sign unsign multiply add ro = ro + rh * rl R1 = R1 + R0H * R4L Instruction to add the product of 16-bit data x 16-bit data to 40-bit data. SUMA The product of the value of bits 31 to 16 of the general-purpose register specified by rh multiplied by the value of bits 15 to 0 of the general-purpose register specified by rl is added to the value of bits 39 to 0 of the general-purpose register specified by ro. The sum is stored in bits 39 to 0 of the general-purpose register specified by ro. The 16-bit value specified by rh and the 40-bit value specified by ro are represented with two's complement, and the 16-bit value specified by rl is a data format of a positive integer value. 39 ro S + 39 rh 32 31 S. 16 15 0 32 31 16 15 . 0 x 39 rl = 39 ro S 32 31 16 15 . 0 32 31 16 15 0 . On the assumption that a decimal point is located between bit 31 and bit 30 of the value of the general-purpose register specified by rh and another decimal point is located below bit 0 of the value of the general-purpose register specified by rl, the product to be added to the value of the generalpurpose register specified by ro is a value with a decimal point located between bit 16 and bit 15, sign-extended to bits 39 to 32 and with bit 0 set to 0. 28 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS SUMA SUMA Trinomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If the addition results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 29 CHAPTER 3 EXPLANATION OF INSTRUCTIONS UUMA Trinomial operation ro = ro + rl * rl' Name of instruction: Mnemonic: Example Explanation Unsign unsign multiply add ro = ro + rl * rl' R1 = R1 + R0L * R4L Instruction to add the product of 16-bit data x 16-bit data to 40-bit data. UUMA The product of the value of bits 15 to 0 of the general-purpose register specified by rl multiplied by the value of bits 15 to 0 of the general-purpose register specified by rl' is added to the value of bits 39 to 0 of the general-purpose register specified by ro. The sum is stored into the general-purpose register specified by ro. The 16-bit values specified by rl and rl' are positive integer values, and the 40-bit value specified by ro is a data format represented with two's complement. 39 ro + 39 rl 32 31 16 15 0 . 32 31 16 15 10 . x 39 rl' = 39 ro 32 31 16 15 10 . 32 31 16 15 0 . On the assumption that a decimal point is located below bit 0 of the values of the general-purpose registers specified by rl and rl', the product to be added to the value of the general-purpose register specified by ro is a value with a decimal point located between bit 1 and bit 0 with bits 39 to 32 and bit 0 set to 0. 30 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS UUMA UUMA Trinomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Cautions 1. The result is treated as two's complement data. 2. If the addition results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 31 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MAS1 Trinomial operation ro = (ro >> 1) + rh * rh' Name of instruction: Mnemonic: Example Explanation 1-bit shift multiply add ro = (ro >> 1) + rh * rh' R1 = (R1 >> 1) + R0H * R4H Instruction to add the product of 16-bit data x 16-bit data to 40-bit data. MAS1 The product of the value of bits 31 to 16 of the general-purpose register specified by rh multiplied by the value of bit 31 to 16 of the general-purpose register specified by rh' is added to the value of bits 39 to 0 of the general-purpose register specified by ro arithmetically shifted to the right by one bit. The sum is stored in bits 39 to 0 of the general-purpose register specified by ro. The 16-bit values specified by rh and rh' and the 40-bit value specified by ro are data formats represented with two's complement. 39 ro S 32 31 30 . 1-bit arithmetic right shift 39 SS 32 31 30 . + 39 rh 32 31 30 S. 16 15 0 16 15 0 16 15 0 x 39 rh' 32 31 30 S. = 39 ro S 32 31 30 . 16 15 0 16 15 0 On the assumption that a decimal point is located between bit 31 and bit 30 of the value of the general-purpose registers specified by rh and rh', the product to be added to the value of the general-purpose register specified by ro is a value with a decimal point located between bit 31 and bit 30, sign-extended to bits 39 to 32 and with bit 0 set to 0. Remark This function is efficient for executing FFT at high speed. 32 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MAS1 MAS1 Trinomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If an arithmetic right shift results in an underflow, the value is not corrected. If 0xFF'FFFF'FFFF is arithmetically shifted to the right in the shift process, the value remains 0xFF'FFFF'FFFF (it is not set to 0x00'0000'0000). User's Manual U13116EJ2V0UM00 33 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MAS16 Trinomial operation ro = (ro >> 16) + rh * rh' Name of instruction: Mnemonic: Example Explanation 16-bit shift multiply add ro = (ro >> 16) + rh * rh' R1 = (R1 >> 16) + R0H * R4H Instruction to add the product of 16-bit data x 16-bit data to 40-bit data. MAS16 The product of the value of bits 31 to 16 of the general-purpose register specified by rh multiplied by the value of bits 31 to 16 of the general-purpose register specified by rh' is added to the value of bits 39 to 0 of the general-purpose register specified by ro arithmetically shifted to the right by 16 bits. The sum is stored in bits 39 to 0 of the general-purpose register specified by ro. The 16bit values specified by rh and rh' and the 40-bit value specified by ro are data formats represented with two's complement. 39 ro S 16-bit arithmetic right shift 39 32 31 30 16 15 0 32 31 16 15 0 S S S S S S S S S. S S S S S S S S + 39 rh 32 31 30 S. 16 15 0 x 39 rh' 32 31 30 S. = 39 ro S 32 31 30 . 16 15 0 16 15 0 On the assumption that a decimal point is located between bit 31 and bit 30 of the value of the specified general-purpose registers specified by rh and rh', the product to be added to the value of the general-purpose register specified by ro is a value with a decimal point located between bit 31 and bit 30, sign-extended to bits 39 to 32 and with bit 0 set to 0. Remark This function is intended for high-speed double precision multiplication. 34 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MAS16 MAS16 Trinomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If an arithmetic right shift results in an underflow, the value is not corrected. If 0xFF'FFFF'FFFF is arithmetically shifted to the right in the shift process, the value remains 0xFF'FFFF'FFFF (it is not set to 0x00'0000'0000). User's Manual U13116EJ2V0UM00 35 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.2 Binomial Operation Instructions Instructions for specifying operations using a multiply-accumulator, ALU, or the barrel shifter. Any two registers can be specified for the operand (inputs) from the general register file. Also available are instructions to specify the immediate value for one input instead of the general-purpose registers. Any one register can be specified for the output destination from the general-purpose register file. The following binomial operation instructions are provided: Multiply Add Immediate add Sub Immediate sub Arithmetic right shift Logical right shift Immediate logical right shift Logical left shift Immediate logical left shift AND Immediate AND OR Immediate OR Exclusive OR Immediate exclusive OR Less than (MPY) (ADD) (IADD) (SUB) (ISUB) (SRA) (SRL) (ISRL) (SLL) (ISLL) (AND) (IAND) (OR) (IOR) (XOR) (IXOR) (LT) Immediate arithmetic right shift (ISRA) 36 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MPY ro = rh * rh' Name of instruction: Mnemonic: Example Explanation Multiply ro = rh * rh' R1 = R0H * R4H MPY Binomial operation Instruction to multiply two 16-bit data. The value of bits 31 to 16 of the general-purpose register specified by rh is multiplied by the value of bits 31 to 16 of the general-purpose register specified by rh'. The product is stored in bits 39 to 0 of the general-purpose register specified by ro. The 16-bit values specified by rh and rh' and the 40-bit value specified by ro are data formats represented with two's complement. 39 32 31 30 S. 16 15 0 rh x 39 rh' 32 31 30 S. = 39 32 31 30 . 16 15 0 0 16 15 0 ro S S S S S S S S On the assumption that a decimal point is located between bit 31 and bit 30 of the value of the general-purpose registers specified by rh and rh', the value to be stored to the general-purpose register specified by ro is a value with a decimal point located between bit 31 and bit 30, signextended to bits 39 to 32 and with bit 0 set to 0. Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution In the following case, bit 31 of the operation result is not a sign. 0x8000 x 0x8000 = 0x00'8000'0000 User's Manual U13116EJ2V0UM00 37 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ADD Binomial operation ro'' = ro + ro' Name of instruction: Mnemonic: Example Explanation Add ro'' = ro + ro' R1 = R0 + R4 ADD Instruction to add two 40-bit data. The value of bits 39 to 0 of the general-purpose register specified by ro is added to that of bits 39 to 0 of the general-purpose register specified by ro'. The sum is stored in bits 39 to 0 of the general-purpose register specified by ro". The 40-bit values specified by ro, ro', and ro'' are data formats represented with two's complement. 39 ro 32 31 16 15 0 + 39 ro' = 39 ro" 32 31 16 15 0 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If the addition results in an overflow, the overflow flag ovf in the error status register ESR is set to 1, but the value is not corrected. 38 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS IADD ro' = ro + imm Name of instruction: Mnemonic: Example Explanation Immediate add ro' = ro + imm (imm = 0 to 0xFFFF (0 to 65535)) R1 = R0 + 0x10 IADD Binomial operation Instruction to add two 40-bit data. The 40-bit immediate value, zero-extended to bits 39 to 16 by specifying the values of bits 15 to 0 using imm, is added to the value of bits 39 to 0 of the general-purpose register specified by ro. The sum is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro 32 31 16 15 0 + 39 32 31 0 = 39 ro' 32 31 30 16 15 0 16 15 imm 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Caution If the addition results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 39 CHAPTER 3 EXPLANATION OF INSTRUCTIONS SUB Binomial operation ro'' = ro - ro' Name of instruction: Mnemonic: Example Explanation Sub ro'' = ro - ro' R1 = R0 - R4 SUB Instruction to subtract 40-bit data from 40-bit data. The value of bits 39 to 0 of the general-purpose register specified by ro' is subtracted from the value of bits 39 to 0 of the general-purpose register specified by ro. The difference is stored in bits 39 to 0 of the general-purpose register specified by ro''. The 40-bit values specified by ro, ro', and ro'' are data formats represented with two's complement. 39 ro 32 31 16 15 0 -- 39 ro' = 39 ro" 32 31 16 15 0 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If the subtraction results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. 40 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ISUB ro' = ro - imm Name of instruction: Mnemonic: Example Explanation Immediate sub ro' = ro - imm (imm = 0 to 0xFFFF (0 to 65535)) R1 = R0 - 0x10 ISUB Binomial operation Instruction to subtract 40-bit data from 40-bit data. The 40-bit immediate value, zero-extended to bits 39 to 16 by setting the value of bits 15 to 0 with imm, is subtracted from the value of bits 39 to 0 of the general-purpose register specified by ro. The difference is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro 32 31 16 15 0 -- 39 32 31 0 = 39 ro' 32 31 16 15 0 16 15 imm 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Caution If the subtraction results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 41 CHAPTER 3 EXPLANATION OF INSTRUCTIONS SRA Binomial operation ro' = ro SRA rl Name of instruction: Mnemonic: Example Explanation Arithmetic right shift ro' = ro SRA rl R1 = R0 SRA R4L SRA Instruction to arithmetically shift 40-bit data to the right. The value of bits 39 to 0 of the general-purpose register specified by ro is arithmetically shifted to the right by the value of bits 5 to 0 of the general-purpose register specified by rl. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. The values of 40 bits of the generalpurpose registers specified by ro and ro' are represented with two's complement and the value of 6 bits of the general-purpose register specified by rl is a data format of a positive integer value. 39 ro S 32 31 16 15 0 Arithmetic right shift 39 ro' S S * * 32 31 16 15 0 An arithmetic right shift is a shift accompanied by sign expansion. Bits 39 to 6 of the generalpurpose register specified by rl are ignored. 42 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS SRA SRA Binomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Cautions 1. If an arithmetic right shift results in an underflow, the value is not corrected. For example, if 0xFF'FFFF'FFFF is arithmetically shifted to the right, the value remains 0xFF'FFFF'FFFF (it is not set to 0x00'0000'0000). 2. If a 40-bit or higher bits are arithmetically shifted to the right, the data is sign-extended to bits 39 to 0. User's Manual U13116EJ2V0UM00 43 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ISRA Binomial operation ro' = ro SRA imm Name of instruction: Mnemonic: Example Explanation Immediate arithmetic right shift ro' = ro SRA imm (imm = 0 to 0x27 (0 to 39)) R1 = R0 SRA 0x10 ISRA Instruction to arithmetically shift 40-bit data to the right. The value of bits 39 to 0 of the general-purpose register specified by ro is arithmetically shifted to the right by the 6-bit immediate value. An arithmetic right shift is a right shift accompanied by sign expansion. Bits 5 to 0 of the immediate value are valid for shift and bits 15 to 6 are ignored. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. The values of 40 bits in the general-purpose registers specified by ro and ro' are represented with two's complement and the 6-bit immediate value is a data format of a positive integer value. 39 ro S 32 31 16 15 0 Arithmetic right shift 39 ro' S S * * 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Caution If an arithmetic right shift results in an underflow, the value is not corrected. For example, if 0xFF'FFFF'FFFF is arithmetically shifted to the right, the value remains 0xFF'FFFF'FFFF (it is not set to 0x00'0000'0000). 44 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS SRL ro' = ro SRL rl Name of instruction: Mnemonic: Example Explanation Logical right shift ro' = ro SRL rl R1 = R0 SRL R4L SRL Binomial operation Instruction to logically shift 40-bit data to the right. The value of bits 39 to 0 of the general-purpose register specified by ro is logically shifted to the right by the value of bits 5 to 0 of the general-purpose register specified by rl. A logical right shift is a shift to insert 0 from the MSB by the shift amount. Bits 39 to 6 of the general-purpose register specified by rl are ignored. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. The values of 40 bits in the general-purpose registers specified by ro and ro' are logical values and the value of 6 bits of the general-purpose register specified by rl is a data format of a positive integer value. 39 ro 32 31 16 15 0 Logical right shift 39 ro' 0 0 * * 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution If a 40-bit or higher logical right shift is specified, 0x00'0000'0000 is set. User's Manual U13116EJ2V0UM00 45 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ISRL Binomial operation ro' = ro SRL imm Name of instruction: Mnemonic: Example Explanation Immediate logical right shift ro' = ro SRL imm (imm = 0 to 0x27 (0 to 39)) R1 = R0 SRL 0x10 ISRL Instruction to logically shift 40-bit data to the right. The value of bits 39 to 0 of the general-purpose register specified by ro is logically shifted to the right by the 6-bit immediate value. A logical right shift is a right shift to insert 0 from the MSB by the shift amount. Bits 5 to 0 of the immediate value are valid for shift and bits 15 to 6 are ignored. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. The values of 40 bits of the generalpurpose registers specified by ro and ro' are logical values and the 6-bit immediate value is a data format of a positive integer value. 39 ro 32 31 16 15 0 Logical right shift 39 ro' 00** 32 31 30 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No 46 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS SLL ro' = ro SLL rl Name of instruction: Mnemonic: Example Explanation Logical left shift ro' = ro SLL rl R1 = R0 SLL R4L SLL Binomial operation Instruction to logically shift 40-bit data to the left. The value of bits 39 to 0 of the general-purpose register specified by ro is logically shifted to the left by the value of bits 5 to 0 of the general-purpose register specified by rl. A logical left shift is a left shift to insert 0 from the LSB by the shift amount. Bits 39 to 6 of the general-purpose register specified by rl are ignored. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. The values of 40 bits of the general-purpose registers specified by ro and ro' are logical values and the value of 6 bits of the general-purpose register specified by rl is a data format of a positive integer value. 39 ro 32 31 16 15 0 Logical left shift 39 ro' 32 31 16 15 0 **00 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution 1. If a 40-bit or higher logical left shift is specified, 0x00'0000'0000 is set. 2. A logical left shift does not generate an overflow. User's Manual U13116EJ2V0UM00 47 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ISLL Binomial operation ro' = ro SLL imm Name of instruction: Mnemonic: Example Explanation Immediate logical left shift ro' = ro SLL imm (0 to 0x27 (0 to 39)) R1 = R0 SLL 0x10 ISLL Instruction to logically shift 40-bit data to the left. The value of bits 39 to 0 of the general-purpose register specified by ro is logically shifted to the left by the 6-bit immediate value. A logical left shift is a left shift to insert 0 from the LSB by the shift amount. Bits 5 to 0 of the immediate value are valid for shift and bits 15 to 6 are ignored. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. The values of 40 bits of the generalpurpose registers specified by ro and ro' are logical values and the 6-bit immediate value is a data format of a positive integer value. 39 ro 32 31 16 15 0 Logical left shift 39 ro' 32 31 16 15 0 **00 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Caution A logical left shift does not generate an overflow. 48 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS AND ro" = ro & ro' Name of instruction: Mnemonic: Example Explanation AND ro" = ro & ro' R1 = R0 & R4 AND Binomial operation Instruction to obtain a logical AND of 40-bit data. The logical AND is obtained from the value of bits 39 to 0 of the general-purpose register specified by ro and the value of bits 39 to 0 of the general-purpose register specified by ro'. The result is stored in bits 39 to 0 of the general-purpose register specified by ro". The values of 40 bits of the generalpurpose registers specified by ro, ro', and ro" are logical values. 39 ro 32 31 16 15 0 AND 39 ro' 32 31 16 15 0 = 39 ro" 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No User's Manual U13116EJ2V0UM00 49 CHAPTER 3 EXPLANATION OF INSTRUCTIONS IAND Binomial operation ro' = ro & imm Name of instruction: Mnemonic: Example Explanation Immediate AND ro' = ro & imm (imm = 0 to 0xFFFF (0 to 65535)) R1 = R0 & 0x10 IAND Instruction to obtain a logical AND of 40-bit data. The logical AND is obtained from the value of bits 39 to 0 of the general-purpose register specified by ro and the 40-bit immediate value, zero-extended to bits 39 to 16 by setting the value of bits 15 to 0 with an instruction. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. Bits 39 to 16 of the general-purpose register specified by ro' are set to 0. The value of the 40 bits specified by ro and ro' and the 16-bit immediate value are logical values. 39 ro 32 31 16 15 0 AND 39 32 31 0 16 15 imm 0 = 39 ro' 32 31 0 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No 50 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS OR ro" = ro | ro' Name of instruction: Mnemonic: Example Explanation OR ro" = ro | ro' R1 = R0 | R4 OR Binomial operation Instruction to obtain a logical inclusive OR of 40-bit data. The logical inclusive OR is obtained from the value of bits 39 to 0 of the general-purpose register specified by ro and the value of bits 39 to 0 of the general-purpose register specified by ro'. The result is stored in bits 39 to 0 of the general-purpose register specified by ro". The values of 40 bits of the ro, ro', and ro" specified general-purpose registers are logical values. 39 ro 32 31 16 15 0 OR 39 ro' 32 31 16 15 0 = 39 ro" 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No User's Manual U13116EJ2V0UM00 51 CHAPTER 3 EXPLANATION OF INSTRUCTIONS IOR Binomial operation ro' = ro | imm Name of instruction: Mnemonic: Example Explanation Immediate OR ro' = ro | imm (imm = 0 to 0xFFFF (0 to 65535)) R1 = R0 | 0x10 IOR Instruction to obtain a logical inclusive OR of 40-bit data. The logical inclusive OR is obtained from the value of bits 39 to 0 of the general-purpose register specified by ro and the 40-bit immediate value, zero-extended to bits 39 to 16 by setting the value of bits 15 to 0 with an instruction. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. Bits 39 to 16 of the general-purpose register specified by ro' become the same as those of the general-purpose register specified by ro. The values of the 40 bits specified by ro and ro' and the 16-bit immediate value are logical values. 39 ro 32 31 16 15 0 OR 39 32 31 0 16 15 imm 0 = 39 ro' 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No 52 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS XOR ro" = ro /\ ro' Name of instruction: Mnemonic: Example Explanation Exclusive OR ro" = ro /\ ro' R1 = R0 /\ R4 XOR Binomial operation Instruction to obtain a logical exclusive OR of 40-bit data. The logical exclusive OR is obtained from the value of bits 39 to 0 of the general-purpose register specified by ro and the value of bits 39 to 0 of the general-purpose register specified by ro'. The result is stored in bits 39 to 0 of the general-purpose register specified by ro". The values of 40 bits of the general-purpose registers specified by ro, ro', and ro" are logical values. 39 ro 32 31 16 15 0 XOR 39 ro' 32 31 16 15 0 = 39 ro" 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No User's Manual U13116EJ2V0UM00 53 CHAPTER 3 EXPLANATION OF INSTRUCTIONS IXOR Binomial operation ro' = ro /\ imm Name of instruction: Mnemonic: Example Explanation Immediate exclusive OR ro' = ro /\ imm (imm = 0 to 0xFFFF (0 to 65535)) R1 = R0 /\ 0x10 IXOR Instruction to obtain a logical exclusive OR of 40-bit data. The logical exclusive OR is obtained from the value of bits 39 to 0 of the general-purpose register specified by ro and the 40-bit immediate value, zero-extended to bits 39 to 16 by setting the value of bits 15 to 0 with an instruction. The result is stored in bits 15 to 0 of the general-purpose register specified by ro'. Bits 39 to 16 of the general-purpose register specified by ro' become the same as those of the general-purpose register specified by ro. The values of the 40 bits specified by ro and ro' and the 16-bit immediate value are logical values. 39 ro 32 31 16 15 0 XOR 39 32 31 0 16 15 imm 0 = 39 ro' 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No 54 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LT ro" = LT (ro, ro') Name of instruction: Mnemonic: Example Explanation Less than ro" = LT (ro, ro') R2 = LT (R1, R4) LT Binomial operation Instruction to compare two 40-bit data. If the value of bits 39 to 0 of the general-purpose register specified by ro is less than the value of bits 39 to 0 of the register specified by ro', 0x00'0000'0001 is stored in bits 39 to 0 of the generalpurpose register specified by ro". If the value of bits 39 to 0 of the general-purpose register specified by ro is greater than or equal to the value of bits 39 to 0 of the register specified by ro', 0x00'0000'0000 is stored in bits 39 to 0 of the general-purpose register specified by ro". The 40bit values specified by ro and ro' are data formats represented with two's complement, whereas the value of ro" can be taken as a boolean number format. 39 ro S 32 31 16 15 0 -- 39 ro' S 32 31 16 15 0 Arithmetic representation if (ro < ro') else {ro" = 1;} {ro" = 0;} User's Manual U13116EJ2V0UM00 55 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LT Binomial operation ro" = LT (ro, ro') LT Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional No Caution When ro' is subtracted from ro, comparison of the size of data where an overflow occurs is correctly performed. The overflow flag will not change. 56 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.3 Monomial Operation Instructions These are instructions for specifying ALU operations. Any one register can be specified for the operand (input) from the general-purpose register file. Any one register can be specified for the output destination from the general-purpose register file. The following monomial operation instructions are provided: Clear Increment Decrement Absolute value (CLR) (INC) (DEC) (ABS) One's complement (NOT) Two's complement (NEG) Clip Round Exponent Put Accumulate add Accumulate sub Divide (CLIP) (RND) (EXP) (PUT) (ACA) (ACS) (DIV) User's Manual U13116EJ2V0UM00 57 CHAPTER 3 EXPLANATION OF INSTRUCTIONS CLR Monomial operation CLR (ro) Name of instruction: Mnemonic: Example Explanation Clear CLR (ro) CLR (R0) Instruction to clear all bits of the general-purpose register specified by ro to 0. CLR 39 ro 32 31 0 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes 58 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS INC ro' = ro + 1 Name of instruction: Mnemonic: Example Explanation Increment ro' = ro + 1 R1 = R1 + 1 INC Monomial operation Instruction to add 1 to 40-bit data. The incremented result of the value of bits 39 to 0 of the general-purpose register specified by ro is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 32 31 16 15 0 ro + 39 32 31 0 16 15 0 1 = 39 ro' 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution If the increment operation results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. (0x7F'FFFF'FFFF + 1 0x80'0000'0000) User's Manual U13116EJ2V0UM00 59 CHAPTER 3 EXPLANATION OF INSTRUCTIONS DEC Monomial operation ro' = ro - 1 Name of instruction: Mnemonic: Example Explanation Decrement ro' = ro - 1 R1 = R1 - 1 DEC Instruction to subtract 1 from 40-bit data. The decremented result of the value of bits 39 to 0 of the general-purpose register specified by ro is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 32 31 16 15 0 ro -- 39 32 31 0 16 15 0 1 = 39 ro' 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution If the decrement operation results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. (0x80'0000'0000 - 1 0x7F'FFFF'FFFF) 60 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ABS ro' = ABS (ro) Name of instruction: Mnemonic: Example Explanation Absolute value ro' = ABS (ro) R2 = ABS (R1) ABS Monomial operation Instruction to obtain the absolute value of 40-bit data. The absolute value of bits 39 to 0 of the general-purpose register specified by ro is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro 32 31 16 15 0 Absolute value 39 ro' 32 31 16 15 0 Arithmetic representation if (ro < 0) {ro' = -ro;} else {ro' = ro;} Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution When the ro specified general-purpose register value is 0x80'0000'0000, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 61 CHAPTER 3 EXPLANATION OF INSTRUCTIONS NOT Monomial operation ro' = Name of instruction: Mnemonic: Example Explanation R2 = One's complement ro' = NOT ~ ro ~ ro ~ R1 Instruction to obtain one's complement of 40-bit data. One's complement of the value of bits 39 to 0 of the general-purpose register specified by ro (with 0 and 1 of each bit inverted) is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro 32 31 16 15 0 One's complement 39 ro' 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes 62 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS NEG ro' = -ro Name of instruction: Mnemonic: Example Explanation Two's complement ro' = -ro R2 = -R1 NEG Monomial operation Instruction to obtain two's complement of 40-bit data. Two's complement (arithmetic negation) of the value of bits 39 to 0 of the general-purpose register specified by ro is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro 32 31 16 15 0 Two's complement 39 ro' 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution When the value of the general-purpose register specified by ro is 0x80'0000'0000, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 63 CHAPTER 3 EXPLANATION OF INSTRUCTIONS CLIP Monomial operation ro' = CLIP (ro) Name of instruction: Mnemonic: Example Explanation Clip ro' = CLIP (ro) R2 = CLP (R1) CLIP Instruction to clip 40-bit data to 32 bits. The value of bits 39 to 0 of the general-purpose register specified by ro and clipped to 32 bits (bits 31 to 0) is stored in bits 39 to 0 of the general-purpose register specified by ro'. The data is signextended to bits 39 to 32 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro S 32 31 16 15 0 Clipping 39 32 31 16 15 0 ro' S S S S S S S S S Arithmetic representation if else if else (ro > 0x00'7FFF'FFFF) (ro < 0xFF'8000'0000) {ro' = ro;} {ro' = 0x00'7FFF'FFFF;} {ro' = 0xFF'8000'0000;} Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution Even if saturation occurred due to CLIP execution, the overflow flag bit will not change. 64 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS RND ro' = ROUND (ro) Name of instruction: Mnemonic: Example Explanation Round ro' = ROUND (ro) R2 = ROUND (R1) RND Monomial operation Instruction to round and clip 40-bit data to 16-bit data. Bits 15 to 0 of the general-purpose register specified by ro are rounded and clipped to 16 bits (bits 31 to 16) and then stored in bits 39 to 0 of the general-purpose register specified by ro'. The rounding of bits 15 to 0 means an addition of 1 to bit 15 only. The data is sign-extended to bits 39 to 32 of the general-purpose register specified by ro' and bits 15 to 0 are set to 0. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 32 31 16 15 0 ro S + 39 32 31 0 Clipping 39 32 31 16 15 0 0 16 15 1 0 0 ro' S S S S S S S S S Arithmetic representation if (ro > 0x00'7FFF'0000) {ro' = 0x00'7FFF'0000;} else if (ro < 0xFF'8000'0000) {ro' = 0xFF'8000'0000;} else {ro' = (ro + 0x8000) & 0xFF'FFFF'0000;} Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution Even if saturation occurred due to RND execution, the overflow flag bit will not change. User's Manual U13116EJ2V0UM00 65 CHAPTER 3 EXPLANATION OF INSTRUCTIONS EXP Monomial operation ro' = EXP (ro) Name of instruction: Mnemonic: Example Explanation Exponent ro' = EXP (ro) R2 = EXP (R1) EXP Instruction to obtain a left shift amount to normalize to 32 bits. The left shift amount (0 to 31) is obtained to normalize the value of bits 31 to 0 of the general-purpose register specified by ro. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. Bits 39 to 5 of the general-purpose register specified by ro' are set to 0. The 32-bit value specified by ro and the 40-bit value specified by ro' are data formats represented with two's complement. 39 ro 32 31 SSS * * * 16 15 0 EXP 39 ro' 32 31 0 16 15 54 0 EXP Here, normalization means the following operation. 39 ro 32 31 30 0 sign 0 * * * * n * * * 0 1 D* * * * * * * 0 D 39 32 31 30 0 1D* * * * * * D 0 * * * * n * * * 0 0 Count the number of bits whose value is the same as the sign bit from bit 30 and lower to find the first bit whose value is different from the sign bit. This number of bits is stored in ro' as n. After this, shift to the left by n. This operation is called "normalization". This keeps the value high-precision if its value is small in case multiplication. The n is set to ro' when EXP instruction is executed. 66 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS EXP EXP Monomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Cautions 1. If the value of the general-purpose register specified by ro is 0x00'8000'0000 or more and 0xFF'7FFF'FFFF or less, the ro' value is not guaranteed. 2. If the value of the general-purpose register specified by ro is 0x00'0000'0000, the ro' value is set to 0x00'0000'0000. 3. If the value of the general-purpose register specified by ro is 0xFF'FFFF'FFFF, the ro' value is set to 0x1F. 4. Bits 31 to 0 of the general-purpose register specified by ro are evaluation targets. User's Manual U13116EJ2V0UM00 67 CHAPTER 3 EXPLANATION OF INSTRUCTIONS PUT Monomial operation ro' = ro Name of instruction: Mnemonic: Example Explanation R2 = R1 Put ro' = ro PUT Instruction to put the 40-bit data of a register into another register. The value of bits 39 to 0 of the general-purpose register specified by ro are stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro S 32 31 16 15 0 PUT 39 ro' S 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes 68 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ACA ro' + = ro Name of instruction: Mnemonic: Example Explanation Accumulate add ro' + = ro R2 + = R1 ACA Monomial operation Instruction to add two 40-bit data. The value of bits 39 to 0 of the general-purpose register specified by ro is added to the value of bits 39 to 0 of the general-purpose register specified by ro'. The sum is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro' S 32 31 16 15 0 + 39 ro S 32 31 16 15 0 = 39 ro' S 32 31 16 15 0 Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution If the addition results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 69 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ACS Monomial operation ro' - = ro Name of instruction: Mnemonic: Example Explanation Accumulate subtract ro' - = ro R2 - = R1 Instruction to subtract 40-bit data from 40-bit data. ACS The value of bits 39 to 0 of the general-purpose register specified by ro is subtracted from the value of bits 39 to 0 of the general-purpose register specified by ro'. The difference is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40-bit values specified by ro and ro' are data formats represented with two's complement. 39 ro' S 32 31 16 15 0 -- 39 ro S 32 31 16 15 0 = 39 ro' S 32 31 16 15 0 70 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS ACS ACS Monomial operation Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution If the subtraction results in an overflow, the overflow flag ovf in the error status register ESR is set to 1. User's Manual U13116EJ2V0UM00 71 CHAPTER 3 EXPLANATION OF INSTRUCTIONS DIV Monomial operation ro' / = ro Name of instruction: Mnemonic: Example Explanation Divide (1 bit) ro' / = ro REP 16 (Example of division in 16-bit range) R2 / = R1 DIV Divide instruction to obtain a quotient bit-wise in one operation. The following operations are carried out using the values of bits 39 to 0 of the general-purpose registers specified by ro' and ro. ro' and ro values with the same sign: ro' - ro ro' and ro values with the different sign: ro' + ro The calculated value is shifted to the left by one bit and one bit of the quotient is inserted into the LSB. The result is stored in bits 39 to 0 of the general-purpose register specified by ro'. The 40bit values specified by ro and ro' are data formats represented with two's complement. 39 32 31 16 15 0 ro' S -- or + 39 32 31 16 15 0 ro S = 39 S Left shift by 1 bit 39 0 0 ro' S 1 or 0 (Depends on result of operation) Set the ro' and ro values as follows: 39 (n + m) bits 0 ro' SS.. Dividend 39 n bits ro SS.. Divisor m bits 0 0 72 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS DIV DIV Monomial operation Repeating the DIV instruction m times produces a quotient and remainder at the following position in the register specified by ro'. 39 n bits ro' SS.. Remainder m bits Quotient Note 0 Dividend Note Quotient = | Divisor | Remark The value of bits 39 to 0 of the general-purpose register specified by ro is the same as the value before operation. Arithmetic representation : if (sign (ro') == sign (ro)) {ro' = ro' - ro;} else {ro' = ro' + ro} if (sign (ro') == 0) {ro' = (ro' << 1) + 1;} else {ro' = ro' << 1;} Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store Yes Inter-register transfer No Branch No Conditional Yes Caution Specification of the same general-purpose register by ro and ro' is forbidden. The absolute value of the dividend should be less than that of devisor. User's Manual U13116EJ2V0UM00 73 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.4 Load/Store Instructions These are instructions to specify 16-bit data transfer between the memory and the general-purpose registers. Load/ store operations consist of parallel load/store for simultaneously specifying an operation instruction, section load/store for specifying the load/store target general-purpose register range, direct addressing load/store for specifying addresses with instructions, and immediate index load/store for specifying the modify value using instructions. Any transfer target (input/output) can be specified from the general-purpose register file. The following are provided as load/store instructions: Parallel load/store Section load/store Direct addressing load/store (LSPA) -- Indirect addressing (LSSE) (LSDA) Immediate value index load/store (LSIM) 74 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSPA Load/Store [ro = *dpx_mod] [ro' = *dpy_mod] [*dpx_mod = rh] [*dpy_mod = rh'] [ro = *dpx_mod] [*dpy_mod = rh] [*dpx_mod = rh] [ro = *dpy_mod] LSPA Name of instruction: Parallel load/store Mnemonic: [ro = *dpx_mod] [ro' = *dpy_mod] [*dpx_mod = rh] [*dpy_mod = rh'] [ro = *dpx_mod] [*dpy_mod = rh] [*dpx_mod = rh] [ro = *dpy_mod] Example Explanation R0 = *DP0++ R1 = *DP4++ Instruction to load/store 16-bit data between the indirectly addressed X/Y memories and a generalpurpose register. It can be coded simultaneously with an operation instruction (except for the immediate value operation). The following four types of coding methods are available: (1) [ro = *dpx_mod] [ro' = *dpy_mod ] The contents of X memory with the address specified by dpx_mod are loaded to the register ro, and the contents of Y memory with the address specified by dpy_mod are loaded to the register ro'. When loading 16-bit data, the memory contents are stored in bits 31 to 16 of the general-purpose register. Bits 39 to 32 are sign-extended, and bits 15 to 0 are set to 0. 15 X memory 39 32 31 16 15 0 0 0 Y memory 39 32 31 16 15 0 0 15 0 ro SSSSSSSS S ro' SSSSSSSS S User's Manual U13116EJ2V0UM00 75 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSPA LSPA Load/Store (2) [*dpx_mod = rh] [*dpy_mod = rh'] The contents of the register rh are loaded to X memory with the address specified by dpx_mod, and the contents of the register rh' are loaded to Y memory with the address specified by dpy_mod. When loading 16-bit data, the contents of the general-purpose register are stored in bits 15 to 0 of the X and Y memories. Bits 39 to 32 and bits 15 to 0 are ignored. 39 rh 32 31 16 15 0 rh' 39 32 31 16 15 0 15 X memory 0 Y memory 15 0 (3) [ ro = * dpx_mod ] [ * dpy_mod = rh ] The contents of X memory with the address specified by dpx_mod are loaded to the register ro, and the contents of the register rh' are loaded to Y memory with the address specified by dpy_mod. When loading 16-bit data, the contents of X memory specified by ro are stored in bits 31 to 16 of the general-purpose register. Bits 39 to 32 are sign-extended, and bits 15 to 0 are set to 0. In the same way, the contents of the general-purpose register specified by rh' are stored in bits 15 to 0 of the Y memory. Bits 39 to 32 and bits 15 to 0 are ignored. 15 X memory 0 rh 39 32 31 16 15 0 39 32 31 ro SSSSSSSS S 16 15 0 0 Y memory 15 0 76 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSPA Load/Store LSPA (4) [*dpx_mod = rh] [ro = *dpy_mod] When loading 16-bit data, the contents of the general-purpose register specified by rh are stored in bits 15 to 0 of the X memory. Bits 39 through 32 and bits 15 through 0 are ignored. In the same way, the contents of Y memory specified by dpy_mod are stored in bits 31 to 16 of the general-purpose register specified by ro. Bits 39 to 32 are sign-extended, and bits 15 to 0 are set to 0. 39 rh 32 31 16 15 0 Y memory 15 0 15 X memory 0 39 32 31 16 15 0 0 ro SSSSSSSS S Remarks 1. Load/store between the X memory and the general-purpose registers and load/store between the Y memory and the general-purpose registers can be specified independently or simultaneously. The data pointer and modifying method can be specified for X and Y independently. 2. The load/store target address is the data pointer value before modification, except for !DPn##. However, the data pointer set by the inter-register transfer instruction and the immediate value set instruction can be specified for the pointer from next-but-one instructions. It must not be specified for the pointer by the instruction just after the above instruction. The data pointer modification result is validated from the succeeding instruction onwards. Execution cycle 1 Instructions that can be described concurrently Trinomial Yes Note Binomial Yes Note Monomial Yes Parallel load/store No Inter-register transfer No Branch No Conditional No Except for the immediate value operation User's Manual U13116EJ2V0UM00 77 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSPA LSPA Load/Store Cautions 1. When load/store between the X memory and a general-purpose register and between the Y memory and a general-purpose register is specified simultaneously, the following combinations of addrx and addry are forbidden. In the PD7701x Family, if one of the following combinations occurs, the bus access error flag is set to 1. Note that this flag is not provided in PD77111 Family devices. Forbidden Combinations [PD77016] External area and external area Peripheral area and peripheral area [PD77015, 77017, 77018, 77018A, 77019] Internal ROM and internal ROM Internal ROM and external area External area and external area Peripheral area and peripheral area [PD77110, 77111, 77112, 77113, 77114] External area and external area Peripheral area and peripheral area 2. The general-purpose register to be loaded from the X memory must not overlap the generalpurpose register to be loaded from the Y memory. 3. The general-purpose register to write back the operation result of the simultaneouslydescribed operation instruction must not overlap the general-purpose register to be loaded from the memory. 4. It is forbidden to load/store by instruction just after a value has been set to the data pointer with the same data pointer value set as an address. Forbidden example 1: Inter-register transfer instruction DP0 = R4L; R0 = *DP0++; Forbidden example 2: Immediate value set instruction DP0 = 0x1234; R0 = *DP0++; 78 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSSE Load/Store [dest = *dpx_mod] [dest' = *dpy_mod] [dest = *dpx_mod] [*dpy_mod = source] [*dpx_mod = source] [dest = *dpy_mod] [*dpx_mod = source] [*dpy_mod = source'] LSSE Name of instruction: Mnemonic: Section load/store [dest = *dpx_mod] [dest' = *dpy_mod] [dest = *dpx_mod] [*dpy_mod = source] [*dpx_mod = source] [dest = *dpy_mod] [*dpx_mod = source] [*dpy_mod = source'] Registers that can be specified are as follows. Any one of these registers may be specified. dest, dest' = {ro, reh, re, rh, rl} source, source' = {re, rh, rl} Example Explanation R0EH = *DP0++ R0L = *DP4++ Instruction to load/store 16-bit data between the indirectly addressed X/Y memory and a generalpurpose register. The range of the general-purpose registers that are the target of the load/store instruction can be specified. (1) There are five ways to load 16-bit data from the memory specified by dpx_mod or dpy_mod to the general-purpose register specified by dest or dest'. (a) When R0 to R7 are specified for dest or dest', the value of the memory specified by dpx_mod or dpy_mod is loaded to bits 31 to 16 of the general-purpose register, the data is sign-extended to bits 39 to 32 and bits 15 to 0 are set to 0. 15 X memory S 39 32 31 ro SSSSSSSS S 0 16 15 0 0 User's Manual U13116EJ2V0UM00 79 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSSE LSSE Load/Store (b) When R0EH to R7EH are specified for dest or dest', the value of the memory specified by dpx_mod or dpy_mod is loaded to bits 31 to 16 of the general-purpose register and the data is signextended to bits 39 to 32. Bits 15 to 0 of the general-purpose register remain unchanged. 15 Memory S 39 32 31 0 16 15 Unchanged 0 reh SSSSSSSS S (c) When R0E to R7E are specified for dest or dest', the low-order 8 bits of the value of the memory specified by dpx_mod or dpy_mod are loaded to bits 39 to 32 of the general-purpose register. Bits 31 to 0 of the general-purpose register remain unchanged. The high-order 8 bits of the memory value are ignored. 70 Memory Invalid Valid 39 32 31 re Unchanged 0 (d) When R0H to R7H are specified for dest or dest', the value of the memory specified by dpx_mod or dpy_mod is loaded to bits 31 to 16 of the general-purpose register. Bits 39 to 32 and bits 15 to 0 of the general-purpose register remain unchanged. 15 Memory 39 32 31 0 16 15 Unchanged 0 rh Unchanged 80 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSSE Load/Store LSSE (e) When R0L to R7L are specified for dest or dest', the value of the memory specified by dpx_mod or dpy_mod is loaded at bits 15 to 0 of the general-purpose register. Bits 39 to 16 of the generalpurpose register remain unchanged. 15 Memory 39 rl Unchanged 16 15 0 0 When 16-bit data is loaded from the Y memory to the same general-purpose register as that to which data is loaded from the X memory simultaneously, the general-purpose register value becomes as follows. X memory and Y memory in the source general-purpose register are interchangeable. * RnEH and RnL; (example: [reh = *dpx_mod] [rl = *dpy_mod]) 15 0 15 Y memory 0 Memory S X memory 39 32 31 reh 16 15 rl 0 ro SSSSSSSS S * RnE and RnH; (example: [re = *dpx_mod] [rh = *dpy_mod]) 7 Memory 0 15 X memory Y memory 0 39 ro re 32 31 rh 16 15 0 Unchanged User's Manual U13116EJ2V0UM00 81 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSSE LSSE Load/Store * RnE and RnL; (example: [re = *dpx_mod] [rl = *dpy_mod]) 7 Memory X memory 0 15 Y memory 0 39 ro re 32 31 16 15 Unchanged rl 0 * RnH and RnL; (example: [rh = *dpx_mod] [rl = *dpy_mod]) 15 Memory X memory 0 15 Y memory 0 39 32 31 rh 16 15 rl 0 ro Unchanged Caution Other combinations are prohibited. (2) There are three ways to store 16-bit data from the general-purpose register specified by source or source' to the memory specified by dpx_mod or dpy_mod. (a) When R0E to R7E are specified for source or source', the value of bits 39 to 32 of the generalpurpose register is stored in the low-order 8 bits of the memory specified by dpx_mod or dpy_mod. The high-order 8 bits of the memory are set to 0. Bits 31 to 0 of the general-purpose register are ignored. 39 source or source' 32 31 16 15 0 15 Memory 0 7 0 82 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSSE Load/Store LSSE (b) When R0H to R7H are specified for source or source', the value of bits 31 to 16 of the general register is stored in the memory specified by dpx_mod or dpy_mod. Bits 39 to 32 and bits 16 to 0 of the general-purpose register are ignored. 39 source or source' 32 31 16 15 0 15 Memory 0 (c) When R0L to R7L are specified for source or source', the value of bits 15 to 0 of the generalpurpose register is stored in the memory specified by dpx_mod or dpy_mod. Bits 39 to 16 of the general-purpose register are ignored. 39 source or source' 16 15 0 15 Memory 0 Remarks 1. Load/store between the X memory and a general-purpose register and load/store between the Y memory and a general-purpose register can be specified independently or simultaneously. 2. The data pointer and its modifying method can be specified for dpx_mod and dpy_mod independently. 3. The load/store target address is the data pointer value before modification except for !DPn##. The data pointer modification result is validated from the succeeding instruction onward. User's Manual U13116EJ2V0UM00 83 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSSE LSSE Load/Store Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Cautions 1. When load/store between the X memory and a general-purpose register and between the Y memory and a general-purpose register is specified simultaneously, the following combinations of addrx and addry are forbidden. In the PD7701x Family, if one of the following combinations occurs, the bus access error flag is set to 1. Note that this flag is not provided in PD77111 Family devices. [Forbidden Combinations] [PD77016] External area and external area Peripheral area and peripheral area [PD77015, 77017, 77018, 77018A, 77019] Internal ROM and internal ROM Internal ROM and external area External area and external area Peripheral area and peripheral area [PD77110, 77111, 77112, 77113, 77114] External area and external area Peripheral area and peripheral area 2. The data pointer that was set with the inter-register transfer instruction or immediate value set instruction can be specified as a pointer with the next-but-one instruction from the above instruction. It must not be specified for the pointer by the instruction just after the above instruction. It is forbidden to load/store by instruction just after a value has been set to the data pointer with the same data pointer value set as an address. Forbidden example 1: Inter-register transfer instruction DP0 = R4L; R0E = *DP0++; Forbidden example 2: Immediate value set instruction DP0 = 0x1234; R0H = *DP0++; 84 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSDA Load/Store dest = *addr *addr = source LSDA Name of instruction: Mnemonic: Direct addressing load/store dest = *addr *addr = source Addresses that can be specified for addr (address): X memory 0 to 0xFFFF (0 to 65535): X (X memory) X memory 0 to 0xFFFF (0 to 65535): Y (Y memory) Registers that can be specified are as follows. Any one of these registers may be specified. dest = {ro, reh, re, rh, rl} source = {re, rh, rl} Example Explanation R0H = *0x1234: X Instruction to load/store 16-bit data between the directly addressed X or Y memory and a generalpurpose register. The range of the general-purpose registers that are the target of the load/store instruction can be specified. (1) There are five ways to load 16-bit data from the memory specified by addr to the generalpurpose register specified by dest. In every case, the value loaded to the general-purpose register will be validated from the next instruction. (a) When R0 to R7 are specified for dest, the value of the memory specified by addr is loaded to bits 31 to 16 of the general-purpose register, the data is sign-extended to bits 39 to 32, and bits 15 to 0 are set to 0. Memory 15 S 0 ro 39 32 31 SSSSSSSS S 16 15 0 0 User's Manual U13116EJ2V0UM00 85 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSDA LSDA Load/Store (b) When R0EH to R7EH are specified for dest, the value of the memory specified by addr is loaded to bits 31 to 16 of the general-purpose register and sign-extended to bits 39 to 32. Bits 15 to 0 of the general-purpose register remain unchanged. 15 S 0 Memory reh 39 32 31 SSSSSSSS S 16 15 Unchanged 0 (c) When R0E to R7E are specified for dest, the low-order 8 bits of the value of the memory specified by addr are loaded to bits 39 to 32 of the general-purpose register. Bits 31 to 0 of the generalpurpose register remain unchanged. The high-order 8 bits of the memory value are ignored. 15 Memory Invalid 87 Valid 0 39 re 32 31 Unchanged 0 (d) When R0H to R7H are specified for dest, the value of the memory specified by addr is loaded to bits 31 to 16 of the general-purpose register. Bits 39 to 32 and bits 15 to 0 of the general-purpose register remain unchanged. 15 Memory 0 rh 39 32 31 Unchanged 16 15 Unchanged 0 (e) When R0L to R7L are specified for dest, the value of the memory specified by addr is loaded to bits 15 to 0 of the general-purpose register. Bits 39 to 16 of the general-purpose register remain unchanged. 15 Memory 0 39 rl Unchanged 16 15 0 86 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSDA Load/Store LSDA (2) There are three ways to store 16-bit data from the general-purpose register specified by source to the memory specified by addr. (a) When R0E to R7E are specified for source, the value of bits 39 to 32 of the general-purpose register is stored in the low-order 8 bits of the memory specified by addr. The high-order 8 bits of the memory are set to 0. Bits 31 to 0 of the general-purpose register are ignored. 39 re 32 31 0 15 Memory 0 87 0 (b) When R0H to R7H are specified for source, the value of bits 31 to 16 of the general-purpose register is stored into the memory specified by addr. Bits 39 to 32 and bits 15 to 0 of the generalpurpose register are ignored. 39 rh 32 31 16 15 0 15 Memory 0 (c) When R0L to R7L are specified for source, the values of bits 15 to 0 of the general-purpose register are stored in the memory specified by addr. Bits 39 to 16 of the general-purpose register are ignored. 39 rl 16 15 0 15 Memory 0 User's Manual U13116EJ2V0UM00 87 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSDA LSDA Load/Store Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No 88 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSIM Load/Store dest = *dp_imm *dp_imm = source LSIM Name of instruction: Mnemonic: Immediate value index load/store dest = *dp_imm *dp_imm = source (imm = 0 to 0xFFFF) Registers that can be specified are as follows. Any one of these registers may be specified. dest = {ro, reh, re, rh, rl} source = {re, rh, rl} Example Explanation R0H = *DP0## 0x10 Instruction to load/store 16-bit data between the indirectly addressed X or Y memory and a generalpurpose register. The range of the general-purpose registers that are the target of the load/store instructions can be specified. (1) There are five ways to load 16-bit data from the memory specified by dp_imm to the generalpurpose register specified by dest. (a) When R0 to R7 are specified for dest, the value of the memory specified by dp_imm is loaded to bits 31 to 16 of the general-purpose register, the data is sign-extended to bits 39 to 32, and bits 15 to 0 are set to 0. 15 S 0 Memory ro 39 32 31 SSSSSSSS S 16 15 0 0 User's Manual U13116EJ2V0UM00 89 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSIM LSIM Load/Store (b) When R0EH to R7EH are specified for dest, the value of the memory specified by dp_imm is loaded to bits 31 to 16 of the general-purpose register, and the data is sign-extended to bits 39 to 32. Bits 15 to 0 of the general-purpose register remain unchanged. 15 S 0 Memory reh 39 32 31 SSSSSSSS S 16 15 Unchanged 0 (c) When R0E to R7E are specified for dest, the low-order 8 bits of the value of the memory specified by dp_imm are loaded to bits 39 to 32 of the general-purpose register. Bits 31 to 0 of the generalpurpose register remain unchanged. The high-order 8 bits of the memory value are ignored. 15 Memory Invalid 87 Valid 0 39 re 32 31 Unchanged 0 (d) When R0H to R7H are specified for dest, the value of the memory specified by dp_imm is loaded to bits 31 to 16 of the general-purpose register. Bits 39 to 32 and bits 15 to 0 of the general-purpose register remain unchanged. 15 Memory 0 rh 39 32 31 Unchanged 16 15 Unchanged 0 (e) When R0L to R7L are specified for dest, the value of the memory specified by dp_imm is loaded in bits 15 to 0 of the general-purpose register. Bits 39 to 16 of the general-purpose register remain unchanged. 15 Memory 0 39 rl Unchanged 16 15 0 90 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSIM Load/Store LSIM (2) There are three ways to store 16-bit data from the general-purpose register specified by source in the memory specified by dp_imm. (a) When R0E to R7E are specified for source, the value of bits 39 to 32 of the general-purpose register is stored in the low-order 8 bits of the memory specified by dp_imm. The high-order 8 bits of the memory are set to 0. Bits 31 to 0 of the general-purpose register are ignored. 39 re 32 31 16 15 0 15 Memory 0 87 0 (b) When R0H to R7H are specified for source, the value of bits 31 to 16 of the general-purpose register is stored in the memory specified by dp_imm. Bits 39 to 32 and bits 15 to 0 of the generalpurpose register are ignored. 39 rh 32 31 16 15 0 15 Memory 0 (c) When R0L to R7L are specified for source, the value of bits 15 to 0 of the general-purpose register is stored in the memory specified by dp_imm. Bits 39 to 16 of the general-purpose register are ignored. 39 rl 32 31 16 15 0 15 Memory Remark 0 The load/store target address is the data pointer value before modification (except for !DPn##). However, the data pointer set by the inter-register transfer instruction and the immediate value set instruction can be specified for the pointer from the next instruction. The data pointer modification result is validated from the succeeding instruction onwards. User's Manual U13116EJ2V0UM00 91 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LSIM LSIM Load/Store Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Caution It is forbidden to load/store by instruction just after a value has been set to the data pointer with the same data pointer value set as an address. Forbidden example 1: Inter-register transfer instruction DP0 = R4L; R0 = *DP0## 0xABCD; Forbidden example 2: Immediate value set instruction DP0 = 0x1234; R0 = *DP0## 0xABCD; 92 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.5 Inter-Register Transfer Instructions This is an instruction to transfer data between general-purpose registers and other registers via the main bus. User's Manual U13116EJ2V0UM00 93 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MOV Inter-register transfer dest = rl rl = source Name of instruction: Mnemonic: Inter-register transfer dest = rl rl = source All registers other than general-purpose registers can be specified for dest and source. Example Explanation DP0 = R0L MOV Instruction to transfer data between a general-purpose register and another register, via the main bus. The value of the register specified by source is transferred bottom-justified to the register specified by dest via the main bus. The following table shows the target registers of this instruction. Register Name General-purpose register Data pointer Index register Modulo register Stack Stack pointer Loop counterNote Loop stack (LSTK) Loop stack pointer Status register Interrupt enable flag stack register Error status register Assembler-Reserved Name R0L to R7L (L part of R0 to R7) DP0 to DP7 DN0 to DN7 DMX, DMY STK SP LC LSR1, LSR2, LSR3 LSP SR EIR ESR Note This register is not specified as dest. 94 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS MOV MOV Inter-register transfer (1) When rl is specified for dest, the value in bits 15 to 0 of the general-purpose register is transferred to the register specified by dest. When the valid bit length of the register specified by dest is m bits (m<16), bits 15 to m of the general-purpose register are ignored. 39 rl 16 15 0 15 dest 0 (2) When rl is specified for source, the value of the register specified by source is transferred to bits 15 to 0 of the general-purpose register. Bits 39 to 16 of the general-purpose register remain unchanged. When the bit length of the source register is n bits (n < 16) as in the ESR, bits 15 to n of the general-purpose register are undefined. 15 source 0 39 rl Execution cycle 1 Unchanged 16 15 0 Instructions that can be described concurrently Trinomial No Note Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No ConditionalNote Yes Limited to DP0 to DP7, DN0 to DN7, DMX, and DMY for dest and source. Cautions 1. If DP0 to DP7 are specified for dest, the transfer result can be specified for the load/store pointer from next-but-one instruction. 2. Modulo index addition should not be executed after a value in the address range 0x8000 to 0xFFFF is transferred to DMX or DMY. 3. When modulo index addition (DPn%%) is executed, transfer a value in the address range 1 to 0x7FFF. When a value of 0, or 0x8000 or higher is transferred, DPn%% does not operate correctly. 4. The value of bit 15 of LC is the loop flag (in/out loop). Do not change this flag. 5. Value between 0 and 0xF can be set for SP. Do not set this register to 0x10 to 0xFFFF. 6. Value between 0 and 4 can be set for LSP. Do not set this register to 0x5 to 0xFFFF. 7. Do not describe the RET or RETI instruction just after the MOV instruction to load from/ store in STK or SP. User's Manual U13116EJ2V0UM00 95 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.6 Immediate Value Set Instruction This is an instruction to set the immediate value to the general-purpose registers and each address operation unit register. 96 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LDI Immediate value set dest = imm Name of instruction: Mnemonic: Immediate value set dest = imm (imm = 0 to 0xFFFF (0 to 65535)) dest = {rl, dp, dn, dm} LDI Example Explanation DP0 = 0x1234 Instruction to set the 16-bit immediate value bottom-justified to the register specified by dest. When R0L to R7L are specified for dest, the immediate value is set at bits 15 to 0 of the generalpurpose register. Bits 39 to 16 remain unchanged. imm 39 dest 15 0 When DP0 to DP7, DN0 to DN7, DMX, or DMY is specified for dest, the 16-bit immediate value becomes the register value. imm 15 dest 0 User's Manual U13116EJ2V0UM00 97 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LDI LDI Immediate value set Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Cautions 1. The set value is validated with the succeeding instruction. However, if DP0 to DP7 are specified for dest, the setting result can be specified for the load/store pointer from next-butone instruction; it must not be specified for the succeeding load/store instruction pointer. 2. When executing modulo index addition, do not specify 0 or one of 0x8000 to 0xFFFF for DMX and DMY. 98 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.7 Branch Instructions These are instructions to specify program branches. Branch instructions consist of branch, jump, subroutine call, and return instructions. Jump Register indirect jump Subroutine call Register indirect subroutine call Return Interrupt return (JMP) (JREG) (CALL) (CREG) (RET) (RETI) User's Manual U13116EJ2V0UM00 99 CHAPTER 3 EXPLANATION OF INSTRUCTIONS JMP Branch JMP imm Name of instruction: Mnemonic: Jump JMP imm (imm = 0 to 0xFFFF (0 to 65535)) JMP Example Explanation JMP 0x1234 Instruction to branch to all addresses in the instruction memory space of the PD77016 Family. A branch is executed in two cycles. Note that no conditional branch instruction, which branches when a flag value is either 0 or 1, is provided for the PD77016 Family. Therefore, when a conditional branch is required, a conditional instruction and a branch instruction should be combined as shown below. Consequently, in this case, the conditional branch is executed in three cycles when the specified condition is satisfied, and in one cycle when unsatisfied. IF (R0 == 0) IF (R2 > 0) JMP LABEL or JMP DP0 (Concerning "JMP DP0", an explanation is given in the description for the JREG instruction on the following page.) Remarks The PD77016 Family JMP and CALL instructions are actually instructions that branch with a relative value in the range of +/- 32 K words. However, the user does not need to consider the relative value because the assembler and linker performs relative address calculations. The user should describe absolute addresses (actual jump destination addresses) in the source program. If code with a relative address is required, put a "$" at the beginning of an operand of the JMP instruction as shown below: JMP JMP $ + 2 ..... Jumps to the next-but-one address. $ - 3 ..... Jumps three addresses before source address. Execution cycle 2 (When used with a conditional instruction: 3 when condition satisfied and 1 when condition not satisfied.) Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional Yes Caution Do not describe the JMP instruction as a repeat target instruction or within three instructions of the loop end. 100 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS JREG JMP dp Name of instruction: Register indirect jump Mnemonic: JMP dp JREG Branch Example Explanation JMP DP0 Instruction to branch to the address of the register value specified by dp (PC dp). The register indirect branch is executed in three cycles. For the coding method of a conditional jump instruction by means of the JREG instruction, refer to the explanation for the JMP instruction. In this case, the conditional branch is executed in three cycles when the specified condition is satisfied, and in one cycle when unsatisfied. Unlike the JMP instruction, the execution cycles of the JREG instruction are unchanged regardless of use alone or together with a conditional instruction. Execution cycle 3 (When used with a conditional instruction, 3 when condition is satisfied and 1 when unsatisfied.) Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional Yes Caution Do not describe the JREG instruction as a repeat target instruction or within three instruction of the loop end. User's Manual U13116EJ2V0UM00 101 CHAPTER 3 EXPLANATION OF INSTRUCTIONS CALL Branch CALL imm Name of instruction: Mnemonic: Subroutine call CALL imm (imm = 0 to 0xFFFF (0 to 65535)) CALL Example Explanation CALL 0x1234 Instruction that branches to a subroutine located at any address in the instruction memory space of the PD77016 Family. A subroutine call is executed in two cycles. This instruction execution increments the stack pointer and stores the address of the next instruction to the stack, then branches to the address specified by the operand (SP SP + 1, STACK PC + 1, PC PC + imm). To execute a conditional branch, a conditional instruction and a branch instruction should be combined as shown below: IF (R0! = 0) CALL LABEL In the same way as the JREG instruction, the conditional branch is executed in three cycles when the specified condition is satisfied, and in one cycle when unsatisfied. Remarks The PD77016 JMP and CALL instructions are actually instructions that branch with a relative value in the range of +/- 32 K words. However, the user does not need to consider the relative value because the assembler and linker performs relative address calculations. The user should code absolute addresses (actual jump destination addresses) in the source program. If code with a relative address is required, put a "$" at the beginning of an operand of the CALL instruction as shown below: CALL $ + 2 ..... Jumps to the next-but-one address. CALL $ - 3 ..... Jumps three addresses before source address. 102 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS CALL CALL Branch Execution cycle 2 (When used with a conditional instruction: 3 when condition satisfied, and 1 when condition not satisfied.) Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional Yes Cautions 1. Do not describe the CALL instruction as a repeat target instruction or within three instructions of the loop end. 2. Do not execute the CALL instruction when the SP value is within 0xF to 0x1F. If it is executed, a stack underflow or overflow occurs, the return address undefined, although the subroutine call is normally executed. 3. Do not describe the unconditional RET instruction or the unconditional RETI instruction, just after a CALL instruction that is combined with a conditional instruction. User's Manual U13116EJ2V0UM00 103 CHAPTER 3 EXPLANATION OF INSTRUCTIONS CREG Branch CALL dp Name of instruction: Mnemonic: Register indirect subroutine call CALL dp CREG Example Explanation CALL DP0 Instruction that executes the same operation as that of the CALL instruction except that the subroutine call address is specified with dp, and three cycles are taken for execution (SP SP + 1, STACK PC + 1, PC reg). Execution cycle 3 (When used with a conditional instruction: 3 when condition satisfied, and 1 when condition not satisfied.) Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional Yes Cautions 1. Do not describe the CALL instruction as a repeat target instruction or within three instructions of the loop end. 2. Do not execute the CALL instruction when the SP value is within 0xF to 0x1F. If it is executed, a stack underflow or overflow occurs, rendering the return address undefined, although the subroutine call is normally executed. 3. Do not describe the unconditional RET instruction or the unconditional RETI instruction just after a CREG instruction that is combined with a conditional instruction. 104 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS RET RET Name of instruction: Mnemonic: Return RET RET Branch Example Explanation RET Instruction that returns processing from the subroutine to the main routine. The processing jumps to the address specified by the stack value indicated by the stack pointer, and then the stack pointer is decremented by one (PC STACK, SP SP - 1). A return is executed in two cycles. To execute a conditional return, a conditional instruction and the RET instruction should be combined in the same way as the JMP and CALL instructions, as shown below: IF (R0 = = 0) RET; Execution cycle 2 (When used with a conditional instruction: 3 when condition satisfied, and 1 when condition not satisfied.) Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional Yes Cautions 1. Executing the RET instruction for purposes other than to exit a subroutine also performs branch and decrements the stack pointer. 2. Do not execute the RET instruction when the SP value is within 0x10 to 0x1F. If it is executed, a stack underflow or overflow occurs, rendering the jump address undefined. 3. Do not describe the RET instruction just after the inter-register transfer instruction to load from/store in STK or SP. 4. Do not describe the RET instruction just after a CALL instruction or CREG instruction that is combined with a conditional instruction. User's Manual U13116EJ2V0UM00 105 CHAPTER 3 EXPLANATION OF INSTRUCTIONS RETI Branch RETI Name of instruction: Mnemonic: Interrupt return RETI RETI Example Explanation RETI Instruction to exit interrupt servicing. The operation of this instruction is the same as that of the RET instruction except that the interrupt enable flag returns to the last condition (PC STACK, SP SP - 1, returns the interrupt enable flag to the last condition). Execution cycle 2 (When used with a conditional instruction: 3 when condition satisfied and 1 when condition not satisfied.) Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional Yes Cautions 1. Do not describe the RETI instruction as a repeat target instruction or within three instructions of the loop end. 2. Executing RETI instruction for purposes other than interrupt servicing also performs branch, decrements the stack pointer, and changes the interrupt enable flag value (for bits 15 to 13 of SR, and left shifts the EIR contents). 3. Do not execute the RETI instruction when the SP value is 0 or within 0x10 to 0x1F. If it is executed, a stack underflow or overflow occurs, rendering the jump address undefined. 4. Do not describe the RETI instruction just after the inter-register transfer instruction to load from/store in STK or SP. 5. Do not describe the RETI instruction just after a CALL instruction or CREG instruction that is combined with a conditional instruction. 6. Do not describe the RETI instruction at the start address of each interrupt source in the vector area. 106 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.8 Hardware Loop Instructions These are instructions to specify repeated execution of one or several instructions. The following hardware loop instructions are provided: Repeat Loop Loop pop (REP) (LOOP) (LPOP) User's Manual U13116EJ2V0UM00 107 CHAPTER 3 EXPLANATION OF INSTRUCTIONS REP Hardware loop REP count Name of instruction: Mnemonic: Repeat REP count count = {1 to 0x7FFF, rl} REP Example REP 0x1234 Explanation Instruction to repeat one instruction. Repeats the succeeding instruction for the number of times specified by the count. During this time, the next instruction is repeatedly fetched. * Start RC count * During repeat PC PC RC RC - 1 * End PC PC + 1 Repeats the shaded instruction the countspecified times. REP count 1 instruction word When the repeat action is completed and the next instruction after the repeated instruction is executed, there will be no overhead. 108 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS REP REP Hardware loop Execution cycle 2 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Cautions 1. A branch instruction (JMP, JREG, CALL, CREG, RET, RETI), or a REP, LOOP, LPOP, STOP, or HALT instruction must not be specified as a repeat target instruction. 2. The loop instruction must not be described as a repeat target instruction. 3. During the execution and decoding cycles of the REP instruction and the repeated instruction, no interrupt is acknowledged. 4. The number of repetitions must not be set to 0 or 0x8000 or higher. User's Manual U13116EJ2V0UM00 109 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LOOP Hardware loop LOOP count { 2 to 255 instruction words }; Name of instruction: Mnemonic: Loop LOOP count { 2 to 255 instruction words }; count = {1 to 0x7FFF, rl} Remarks Example LOOP 0x1234 R1 = R0 + R4 *DP1++ = R1 Explanation The " { " " } " should also be entered. { R0 = *DP0++ R4 = *DP4++; LOOP }; Instruction to repeat two or more instructions. For one instruction repeat, use the REP instruction. Repeats the instructions from the succeeding instruction (loop starting address) to the instruction (loop ending address) just before the loop end pseudo-instruction ( } ) for the number of times specified by the count. The difference between the loop starting address and the loop ending address can be set within the range of 2 to 255. Operations during the LOOP instruction execution are as follows: * Start LSP LSP + 1 LSR1 LSA LSR2 LEA LSR3 LC LSA PC + 1 LEA PC + RLE (loop end relative address) LC count * Loop end instruction fetch (during loop) LC LC - 1 PC LSA * Loop end instruction fetch (loop end) PC PC + 1 LC LSR3 LEA LSR2 LSA LSR1 LSP LSP - 1 LOOP count { Repeats the shaded instructions the countspecified times. }; 2 to 255 instruction words When branching from the loop ending address to the loop starting address, and when executing the instruction just behind the loop end pseudo-instruction after completion of the loop operation, there will be no overhead. During the execution and decoding cycles of the LOOP instruction and the fetching cycle of the loop end instruction, no interrupt is acknowledged. 110 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LOOP LOOP Hardware loop Execution cycle 2 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Cautions 1. Do not describe branch instructions (JMP, JREG, CALL, CREG, RET, RETI), or the REP, LOOP, LPOP, STOP, or HALT instruction, and a transfer instruction from LC within three instructions of the loop end. Care must be taken not to overlap the loop end with a loop end specified by another loop instruction. Forbidden example 1: LOOP 0x1234 { : : Branch instruction }; Forbidden example 2: LOOP 0x1234 { : : LOOP 0x2345 { : : }; }; 2. A transfer instruction from LC must not be described as the loop start. 3. Do not describe the repeat instruction within three instructions of the loop end. 4. Do not execute the LOOP instruction when LSP is 4 to 7, or a loop stack underflow or overflow may occur. 5. The number of repetitions must not be set to 0 or 0x8000 or higher. User's Manual U13116EJ2V0UM00 111 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LPOP Hardware loop LPOP Name of instruction: Mnemonic: Loop pop LPOP LPOP Example LPOP Explanation Discards the present loop information and transfers the values of the loop stack indicated by the loop stack pointer to LC, LEA, and LSA. Decrements the value of the loop stack pointer. Operations during LOOP instruction execution are as follows: LOOP count { LC LSR3 LEA LSR2 LSA LSR1 LSP LSP - 1 } jmp $ + 2 _LOOP_LPOP: lpop IF (xxx) jmp _LOOP_LPOP; 112 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS LPOP LPOP Hardware loop Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Cautions 1. Do not describe the LPOP instruction within three instructions of the loop end. 2. The LPOP instruction should not be described as a repeat target instruction. 3. Do not execute the LPOP instruction when LSP is 0 or 5 to 7. If it is executed, loop stack underflow or overflow occurs. 4. The LPOP instruction does not terminate a loop. It only decreases the loop stack pointer (LSP). User's Manual U13116EJ2V0UM00 113 CHAPTER 3 EXPLANATION OF INSTRUCTIONS 3.9 Control Instructions These are instructions to specify program control. The following control instructions are provided: No operation Halt Stop Condition (NOP) (HALT) (STOP) (COND) Forget interrupt (FINT) 114 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS NOP NOP Name of instruction: Mnemonic: No operation NOP NOP Control Example NOP Explanation Only updates the value of PC and executes nothing. This instruction is used to consume one instruction cycle for timing. Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No User's Manual U13116EJ2V0UM00 115 CHAPTER 3 EXPLANATION OF INSTRUCTIONS HALT Control HALT Name of instruction: Mnemonic: Halt HALT HALT Example HALT Explanation Stops the operation of the PD77016 Family. Remarks 1. In HALT mode, the pins, registers, and internal memory of the device retain the statuses immediately before the HALT mode is set (refer to PD7701x Family User's Manual Architecture or PD77111 Family User's Manual Architecture). 2. This mode is released by using an external/internal interrupt (which is not masked) or hardware reset. Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Caution Do not describe the HALT instruction as a repeat target instruction or within three instructions of the loop end. 116 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS STOP STOP Name of instruction: Mnemonic: Stop STOP STOP Control Example STOP Explanation Stops operation of the clock circuit and PLL of the PD77016 Family (excluding the PD77016). Remarks 1. In the STOP mode, the device pins retain the statuses immediately before the STOP mode is set (refer to PD7701x Family User's Manual Architecture or PD77111 Family User's Manual Architecture). 2. The STOP mode can be released by means of hardware reset or WAKEUP pin inputNote. Note Releasing the STOP mode by means of WAKEUP pin input is available only for the PD77111 Family. Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No Cautions 1. Do not describe the STOP instruction as a repeat target instruction or within three instruction of the loop end. 2. In STOP mode, the output pin statuses are initialized by hardware reset. The output pin statuses are not assured and go into a high-impedance state until the PLL becomes stable. 3. A NOP instruction must be inserted immediately before the STOP instruction for releasing the STOP mode by means of WAKEUP pin input in PD77111 Family devices. Example) nop; Required stop; STOP instruction assuming release by means of WAKEUP pin input User's Manual U13116EJ2V0UM00 117 CHAPTER 3 EXPLANATION OF INSTRUCTIONS FINT Control FINT Name of instruction: Mnemonic: Forget interrupt FINT FINT Example FINT Explanation Discards all existing interrupt requests. This instruction is used to synchronize the program with the generation of the specified interrupt factor when the servicing order of interrupts to be processed is limited. Execution cycle 1 Instructions that can be described concurrently Trinomial No Binomial No Monomial No Parallel load/store No Inter-register transfer No Branch No Conditional No 118 User's Manual U13116EJ2V0UM00 CHAPTER 3 EXPLANATION OF INSTRUCTIONS COND IF (ro cond) Name of instruction: Mnemonic: Condition IF (ro cond) COND Conditions that can be described in cond (condition): EVER: ==0: !=0: >0: <0: <=0: >=0: ==EX: !=EX: Example Unconditional (top description not necessary) =0 0 >0 <0 0 0 Extension (bits 39 to 31 are a mixture of 0 and 1) Without extension (bits 39 to 31 are all 0 or all 1) IF (R1 >= 0) R0 = R0 + 1 Explanation Judges the condition. The top specified general-purpose register is evaluated as 40-bit data represented with two's complement. Executes the instruction described in the same statement if the condition is true. If the condition is false, there is no operation. Execution cycle Number of cycles of the instruction described simultaneously (when the condition was true), or 1 (when the condition was false) Instructions that can be described concurrently Trinomial No Binomial No Monomial Yes Parallel load/store No Inter-register transfer Yes Branch Yes Conditional No User's Manual U13116EJ2V0UM00 119 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS This section describes the features of each instruction category. Table A-1 lists the formats of instruction words. Table A-1. Formats of Instruction Words 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 op1 01 0 1 1 opcode 1 opcode op2 op1 op1 op1 sufy suf suf 0 dest1 1 dest1 0 source2 1 source2 - dest1 - - - - - op3 op2 op2 op2 - dx dy dpx dx dy dpx - - - - - modix modix - - - rx (rxh) rx (rxh) - - - 87 dpy dpy 65 4 32 1 0 modiy modiy ry (ryh) ry (ryh) top 1 0 opcode 0 1 opcode 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 01 01 00 11 11 11 11 11 11 01 01 00 11 11 10 10 0 1 sufx 0 reg 1 reg - cond 01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - imm modix regx dpy modiy regy - dx dy dpx -d d 0 0 1 1 0 -1 direct imm - - - - - - - - xy - dp 1 source1 1 source1 1 dest2 1 dest2 0- - - - - - - - - - - - - - - - - - - - - - - - - - - cond - - - - - top - top - - - - - - - - cond - - - imm imm cond top top top 0 dest2 1 jc - 0 jc - 1 rt - 1- 0- 1- 0- - - - Relative address - - - - - - - - - - - - - dp - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - cond - cond - 0 imm (Repeated times) - - - - - - - - - - - - - - rl - Loop end relative address 0 imm (Repeated times) - Loop end relative address - - - - - - - - - - - - - rl Remark -: Unused bits 120 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.1 Three-Operand Instructions A three-operand instruction uses three operands when an operation is executed between the MAC and ALU. Trinomial and binomial instructions fall into this category, and are executed in the following formats: * Format of trinomial instruction OP3 = OP3 opm op1 OP1 op2 OP2; where, OP1: OP2: OP3: opm: op1: op2: 1st operand (operation operand) 2nd operand (operation operand) 3rd operand (operation operand and result operand) Locally modifies OP3 under MSFT operation direction. Either "no direction", ">>1 (1-bit arithmetic right shift)", or ">>16 (16-bit arithmetic right shift)". ALU operation direction. "+" or "-". MAC operation direction. Always "*". * Format of binomial instruction (1) OP3 = OP1 op OP2; (2) OP3 = oplt (OP1, OP2); where, OP1: 1st operand (operation operand) OP2: 2nd operand (operation operand) OP3: 3rd operand (result operand) op: ALU or MAC operation direction oplt: ALU operation direction. Always "LT". All binomial instructions, except LT (Less Than), are described in format (1). Only the LT instruction is described in format (2). With a three-operand instruction, parallel load and store instructions can be described simultaneously, so that data can be exchanged between the X or Y memory and a general-purpose register while an operation of the ALU or MAC is executed. Figure A-1 shows the instruction word format of three-operand instructions. User's Manual U13116EJ2V0UM00 121 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS Figure A-1. Three-Operand Instruction Format XY parallel load/store (operation register op [ memory) can be described simultaneously. [rx = *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] [ry = *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] ][ ] [*dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] = rxh] [*dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] = ryh] 28 27 opcode 24 23 op2 21 20 op3 18 17 16 15 14 13 dx dy dpx modix 11 10 rx (rxh) 87 dpy 65 modiy 32 ry (ryh) 0 31 30 1 op1 opcode op3 = lt (op1,op2) op3 = op1h*op2h op3 = op3 + op1h*op2h op3 = op3 - op1h*op2h op3 = op3 + op1h*op2l op3 = op3 + op1l*op2l op3 = op3 >> 1 + op1h*op2h op3 = op3 >> 16 + op1h*op2h op3 = op1 + op2 op3 = op1 - op2 op3 = op1 & op2 op3 = op1 | op2 op3 = op1 ^ op2 op3 = op1 sra op2l op3 = op1 srl op2l op3 = op1 sll op2l op1, op2, op3 r0 (r0h, r0l) r1 (r1h, r1l) r2 (r2h, r2l) r3 (r3h, r3l) r4 (r4h, r4l) r5 (r5h, r5l) r6 (r6h, r6l) r7 (r7h, r7l) 122 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.2 Two-Operand Instructions Only the monomial instructions of the ALU (including NOP) are classified as two-operand instructions. * Format of monomial instruction (1) opn (2) OP2 = OP1 op 1; (3) OP2 opu = OP1; (4) OP2 = opl OP1; (5) OP2 = opf (OP1); where OP1: 1st operand (operation operand) OP2: 2nd operand (result operand) opn: "NOP" only op: opl: opf: Operation direction to ALU. "+" or "-". Operation direction to ALU. "-" or " ~ ". Operation direction to ALU. "CLIP", "ROUND", or "EXP". opu: Operation instruction to ALU. Refer to the figure below. Caution "NOP" is a direction to the ALU and does not mean that the entire instruction word is "NOP". With a two-operand instruction, either of a parallel load/store instruction or a conditional instruction can be described simultaneously so that data can be exchanged between the X or Y memory and a general-purpose register while the ALU or MAC is executing an operation, or so that an ALU or MAC operation can be executed when a given condition is satisfied. Figure A-2 shows the instruction word format of two-operand instructions. User's Manual U13116EJ2V0UM00 123 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS Figure A-2. Two-Operand Instruction Format XY parallel load/store (operation register op memory) can be described simultaneously. [rx = *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] [ry = *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] [ ][ ] [*dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] = rxh] [*dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##)] = ryh] 28 27 1 1 1 opcode 24 23 op1 21 20 op2 18 17 16 15 14 13 dx dy dpx modix 11 10 rx (rxh) 87 dpy 65 modiy 32 ry (ryh) 0 31 0 Condition can be described simultaneously. [if (top cond)] op 31 0 1 1 28 27 0 opcode 24 23 op1 21 20 op2 op1, op2 r0 r1 r2 r3 r4 r5 r6 r7 18 17 - - - - - - - - - - 7 6 32 top 0 - cond opcode nop clr (op2) op2 = op1 + 1 op2 = op1 - 1 op2 = abs (op1) ~ op2 = op1 op2 = -op1 op2 = clip (op1) op2 = round (op1) op2 = exp (op1) op2 = op1 op2 / = op1 op2 + = op1 op2 - = op1 124 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.3 Immediate Value Operation Instructions Only the immediate binomial operation instruction of the ALU falls into the category of immediate value operation instructions. * Binomial operation instruction (immediate operation) OP2 = OP1 op imm; where, OP1: 1st operand (operation operand) OP2: 2nd operand (result operand) op: ALU operation direction. Refer to Figure A-3 below. imm: 16-bit immediate data No other instruction can be described simultaneously with an instruction in this category. Figure A-3 shows the instruction word format of immediate value operation instructions. Figure A-3. Immediate Value Operation Instruction Format op imm 31 0 1 0 28 27 1 opcode 24 23 op1 21 20 op2 op1, op2 r0 r1 r2 r3 r4 r5 r6 r7 18 17 16 15 - - imm imm 0 to 3fh/ffffh 0 opcode op2 = op1 + imm op3 = op1 - imm op2 = op1 & imm op2 = op1 | imm op2 = op1 ^ imm op2 = op1 sra imm op2 = op1 srl imm op2 = op1 sll imm User's Manual U13116EJ2V0UM00 125 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.4 Load/Store Instructions Load/store instructions can be classified into the following four types: * Parallel load/store instruction This instruction loads or stores 16-bit data between X or Y memory and a general-purpose register. When accessing the memory with this instruction, only the indirect addressing mode using DPn (n = 0 to 7) is valid. The important point about this instruction is that it can be described with any of the following operation instructions: * Trinomial operation instructions * Binomial operation instructions (except immediate binomial operation) * Monomial operation instructions Therefore, preparing data in a general-purpose register for the next operation while executing an operation can be executed with a single instruction. * Partial load/store instruction This instruction loads or stores 16-bit data between the X or Y memory and a general-purpose register. When accessing the memory with this instruction, only the indirect addressing mode using DPn (n = 0 to 7) is valid. The important points about this instruction are as follows: * Any part of a general-purpose register can be specified for loading or storing data. * 16-bit data can be loaded simultaneously from the X and Y memories (32-bit data load) to two parts of a general-purpose register. * No other instruction can be described with this instruction. * Direct addressing load/store instruction This instruction directly specifies the type of data memory and an address in the instruction word. The important points about this instruction are as follows: * The type of data memory and an address can be directly described in the instruction. * Data can be loaded (from memory to a general-purpose register) to any one or two parts (Rn, RnEH: n = 0 to 7) of a general-purpose register. * Data can be stored (from a general-purpose register to memory) from any part of a general-purpose register. * The X and Y memories cannot be accessed at the same time. * No other instruction can be described simultaneously with this instruction. * Immediate modify load/store instruction This instruction employs the indirect addressing mode using DPn. However, DPn is modified by immediate data, instead of DNn, after access. The important points about this instruction are as follows: * Data modifying DPn is directly described in the instruction. * Data can be loaded (from memory to a general-purpose register) to any one or two parts of a general-purpose register (Rn, RnEH: n = 0 to 7). * Data can be stored (from a general-purpose register to memory) in any part of a general-purpose register. * The X and Y memories cannot be accessed at the same time. * No other instruction can be described simultaneously with this instruction. 126 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS Figure A-4 shows the instruction word format of load/store instructions. Figure A-4. Load/Store Instruction Format (1/2) XY parallel load/store (operation register memory) [op] x load/store nop y load/store nop rx = *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##) ry = *dp (*dp++, *dp - -, *dp##, *dp%%, *!dp##) *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##) = rxh *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##) = ryh 31 30 1 op1 28 27 opcode 24 23 op2 op1 21 20 op3 op2 18 17 16 15 14 13 dx dy dpx dx dy dpx modix modix 11 10 rx (rxh) rx (rxh) 87 dpy dpy 65 modiy modiy 32 ry (ryh) ry (ryh) 0 0 1 1 1 opcode dx, dy *dp = rxh (ryh) rx (ry) =*dp rx (rxh), ry (ryh) r0 (r0h) r1 (r1h) r2 (r2h) r3 (r3h) r4 (r4h) r5 (r5h) r6 (r6h) r7 (r7h) dpx, dpy dp0, dp4 dp1, dp5 dp2, dp6 dp3, dp7 modix, modiy nop *dpx (y) *dpx (y)++ *dpx (y)- - *dpx (y)## *dpx (y)%% *idpx (y)## Partial load/store x load/store nop regxs = *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##) *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##) = regxs 31 0 1 0 28 27 26 25 01 1 sufx 23 22 sufy regx, regy r0suf r1suf r2suf r3suf r4suf r5suf r6suf r7suf y load/store nop regys = *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##) *dp (*dp++, *dp- -, *dp##, *dp%%, *!dp##) = regys 11 10 regx 87 dpy 65 modiy 32 regy 0 20 19 18 17 16 15 14 13 - - dx dy dpx dpx, dpy dp0, dp4 dp1, dp5 dp2, dp6 dp3, dp7 modix sufx + dx, sufy + dy *dp = rx (y) l *dp = rx (y) h *dp = rx (y) e rx (y) l = *dp rx (y) h = *dp rx (y) e = *dp rx (y) eh = *dp rx (y) = *dp modix, modiy nop *dpx (y) *dpx (y)++ *dpx (y)- - *dpx (y)## *dpx (y)%% *idpx (y)## User's Manual U13116EJ2V0UM00 127 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS Figure A-4. Load/Store Instruction Format (2/2) Direct addressing load/store regs = *direct: x (y) [ ] *direct: x (y) = regs 31 0 1 0 28 27 26 25 01 0 reg reg r0suf r1suf r2suf r3suf r4suf r5suf r6suf r7suf 23 22 suf xy x y 20 19 18 17 16 15 xy - -d direct 0 suf + d *dp = regl *dp = regh *dp = rege regl = *dp regh = *dp rege = *dp regeh = *dp reg = *dp direct 0 to ffffh Immediate value modify load/store rs = *dp##imm [ ] *dp##imm = rs 31 0 1 0 28 27 26 25 00 1 reg reg r0suf r1suf r2suf r3suf r4suf r5suf r6suf r7suf 23 22 suf 20 19 dp dp dp0 dp1 dp2 dp3 dp4 dp5 dp6 dp7 17 16 15 d imm im 0 to ffffh 0 suf + d *dp##imm = regl *dp##imm = regh *dp##imm = rege regl = *dp##imm regh = *dp##imm rege = *dp##imm regeh = *dp##imm reg = *dp##imm 128 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.5 Inter-Register Transfer Instruction This instruction transfers data between a general-purpose register and a register connected to the main bus. The important points about this instruction are as follows: * A general-purpose register must always be described at one end of transfer (i.e., as destination or source). * Any register connected to the main bus can be specified as the destination or source. * Because a conditional instruction can be described at the same time, conditional transfer can be executed. Remark This instruction cannot be used to transfer data between two general-purpose registers. Use the monomial instruction PUT to transfer data between general-purpose registers. Figure A-5 shows the instruction word format of the inter-register transfer instruction. Figure A-5. Inter-Register Transfer Instruction Format [if cond] dest = source 31 0 0 0 0 0 0 1 1 1 28 27 26 25 1 11 11 11 23 22 21 0 dest1 1 dest1 0 source2 1 source2 17 16 15 0 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 7 - 6 - - - 32 top - - top - - - - - - - 0 0011 1 source1 1 source1 1 dest2 1 dest2 - cond - cond - - - source1, dest2 r0l r1l r2l r3l r4l r5l r6l r7l dest1, source2 dp0 dp1 dp7 dn0 dn1 dn7 dmx dmy sr eir stack sp lc Note lsp lsr1 lsr2 lsr3 esr Note source2 only Unconditional Conditional User's Manual U13116EJ2V0UM00 129 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.6 Immediate Value Set Instruction This instruction sets immediate data to a general-purpose register or addressing register. The important points about using this instruction are as follows: * Specify the L part (R7L to R0L), DPn, PNn, or DMX/Y of a general-purpose register. * No other instruction can be described at the same time. Figure A-6 shows the instruction word format of the immediate value setting instruction. Figure A-6. Immediate Value Set Instruction Format reg = imm 31 0 0 1 28 27 26 25 1 0- - 11 0 dest2 dest1 dp0 dp1 dp7 dn0 dn1 dn7 dmx dmy 23 22 - dest1 - - imm 0 to ffffh - - - 17 16 15 0 -1 imm imm 0 0011 dest2 r0l r1l r2l r3l r4l r5l r6l r7l 130 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.7 Branch Instructions Branch instructions can be classified into the following three types: * Relative address jump/relative address call Instructions of this type implement branching by adding (subtracting) the difference from the targeted address to (from) the current PC value. The difference is given as a 16-bit two's complement; therefore, execution can be branched over the entire 64-Kword instruction memory space. The important points about this instruction are as follows: * The operand is a 16-bit two's complement that indicates a difference from the branch destination address. (Note, however, that the numeric value of the targeted address is described directly or as a label in assembly language.) * A conditional instruction can be described at the same time. * Indirect jump/indirect call The branch destination address is given by using a register (DPn). At this time, the specified value of DPn is directly set to the PC. The important points about this instruction are as follows: * The operand is DPn (n: 0 to 7). * A conditional instruction can be described at the same time. * Return/interrupt return The branch destination address is the difference from the data saved to STK (stack) and is added to (subtracted from) the current PC value. * There is no explicit operand, but STK is specified as an implicit operand. The value of STK is added to (subtracted from) the current PC value as a two's complement. * A conditional instruction can be described at the same time. Figure A-7 shows the instruction word format of branch instructions. User's Manual U13116EJ2V0UM00 131 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS Figure A-7. Branch Instruction Format Relative address jump/relative address call [if cond] jmp/call imm 31 0 jc br call 0 1 28 27 26 25 24 23 22 01 1 jc - - Jump/call relative address 7 6 cond 32 top 0 Indirect jump/indirect call [if cond] jmp/call dp 31 0 jc jp callr 0 1 28 27 26 25 24 01 0 jc - dp dp0 dp1 dp2 dp3 dp4 dp5 dp6 dp7 - - - 20 19 - dp 17 16 - - - - - - - - - 7 6 32 top 0 - cond Return/interrupt return [if cond] return/returni 31 0 rt ret reti 0 1 28 27 26 25 24 00 1 rt - - - - - - - - - - - - - - - - - 7 6 32 top 0 - cond 132 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.8 Hardware Loop Instructions Hardware loop instructions can be classified into the following two types: * Repeat instruction This instruction repeatedly executes a specified instructionNote. The important points about this instruction are as follows: * The number of times the specified instruction is to be repeated can be described directly in the repeat instruction, or as the L part (RnL: n = 0 to 7) of a general-purpose register. * No other instruction can be described at the same time. * Loop instruction This instruction repeatedly executes a group of instructions. One group can consist of two to 255 instructions (see Note). The important points about this instruction are as follows: * The number of times the specified instructions are to be repeated can be described directly in the repeat instruction, or as the L part (RnL: n = 0 to 7) of a general-purpose register. * No other instruction can be described at the same time. Note "Instruction" in this case is in units of one instruction word, and does not mean a function instruction, which is a field element in an instruction word. Figure A-8 shows the instruction word format of hardware loop instructions. User's Manual U13116EJ2V0UM00 133 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS Figure A-8. Hardware Loop Instruction Format Repeat instruction repeat count 31 0 0 0 28 27 26 25 11 1- - - - - - - - - 16 15 14 - 0 imm 0 imm 1to7fffh repeat rl 31 0 rl r0l r1l r2l r3l r4l r5l r6l r7l 0 0 28 27 26 25 11 0- - - - - - - - - - - - - - - - - - - - - - 32 - rl 0 Loop instruction loop imm { } 31 0 0 0 28 27 26 25 24 23 10 1- 16 15 14 0 - Loop end relative address 0 imm imm 1to7fffh loop rl { } 31 0 rl r0l r1l r2l r3l r4l r5l r6l r7l 0 0 28 27 26 25 24 23 10 0- 16 15 - - - - - - - - - - - - 32 - rl 0 - Loop end relative address 134 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.9 CPU Control Instructions Instructions of this category do not use an operand. No other instruction can be described with these instructions. Figure A-9 shows the instruction word format of CPU control instructions. Figure A-9. CPU Control Instruction Format nop 31 0 0 0 28 27 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 halt 31 0 0 0 28 27 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 lpop 31 0 0 0 28 27 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 fint 31 0 0 0 28 27 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 stop (except for PD77016) 31 28 27 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 User's Manual U13116EJ2V0UM00 135 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS A.10 Conditional Instructions A conditional instruction is meaningful when used in combination with other function instructions. * Description format IF (ro cond) other instruction; where ro: any general-purpose register (R7 to R0) cond: condition. The following conditions can be described: ==0: !=0: >0: <0: >=0: <=0: Judges =0 Judges 0 Judges >0 Judges <0 Judges 0 Judges 0 ==ex: Extension (bits 39 to 31 are mixed 0 and 1) !=ex: Without extension (bits 39 to 31 are all 0 or all 1) * Other instructions that can be described in combination Any of the following instructions can be described in combination with the conditional instruction: * Monomial operation instruction * Inter-register transfer instruction * Branch instruction Figure A-10 shows the instruction word format of conditional instructions. 136 User's Manual U13116EJ2V0UM00 APPENDIX A CLASSIFICATION OF INSTRUCTION WORDS Figure A-10. Conditional Instruction Format Conditional operation if (cond) op 31 0 1 1 28 27 0 opcode 24 23 op1 21 20 op2 18 17 - - - - - - - - - - 7 6 32 top 0 - cond Register-to-register transfer if (cond) dest = source 31 28 27 26 25 23 22 21 0 dest1 0 source2 17 16 15 0 1 - - - - - - - - - - - - - - - - 7 6 32 top top 0 0 0 0 0 1 1 11 11 1 source1 1 dest2 - cond - cond Relative address jump/relative address call if (cond) jmp/call imm 31 0 0 1 28 27 26 25 24 23 22 01 1 jc - - Branch/call relative address 7 6 cond 32 top 0 Indirect jump/indirect call if (cond) jmp/call dp 31 0 0 1 28 27 26 25 24 01 0 jc - - - - 20 19 17 16 - dp - - - - - - - - - 7 - 6 cond 32 top 0 Return/interrupt return if (cond) return/returni 31 0 top r0 r1 r2 r3 r4 r5 r6 r7 ==0 !=0 >0 <=0 >=0 <0 ==ex !=ex 0 1 28 27 26 25 24 00 1 rt - cond ever - - - - - - - - - - - - - - - - 7 6 32 top 0 - cond User's Manual U13116EJ2V0UM00 137 APPENDIX B INSTRUCTION SETS Simultaneously Describable Flag Instruction Name Mnemonic Operation Trinomial Binomial Monomial Load/store Transfer Immediate Branch Loop Condition Group OV Page Multiply add ro = ro + rh*rh' ro ro ro ro ro + rh*rh' ro - rh*rh' ro + rh*rl ro + rl*rl' 1 1 1 1 24 26 28 30 Multiply subtract ro = ro - rh*rh' Sign-unsign multiply add Trinomial Unsign-unsign multiply add 1-bit shift multiply add 16-bit shift multiply add Multiply Add Immediate add ro = ro + rh*rl (rl is positive integer) ro = ro + rl*rl' (rl and rl' are positive integer) ro = (ro >> 1) + rh*rh' ro ro + rh*rh' 2 ro + rh*rh' 2 16 rh*rh' ro + ro' 1 32 ro = (ro >> 16) + rh*rh' 34 ro ro ro" ro = rh*rh' ro" = ro + ro' ro' = ro + imm 37 1 1 38 39 ro' ro + imm (imm = 1) ro" ro - ro' Sub Immediate sub Arithmetic right shift Immediate arithmetic right shift ro" = ro - ro' ro' = ro - imm 1 1 40 41 42 44 ro' ro - imm (imm = 1) ro' ro' ro >> rl ro >> imm ro' = ro SRA rl ro' = ro SRA imm Binomial Logical right shift ro' = ro SRL rl Immediate logical ro' = ro SRL imm right shift Logical left shift ro' = ro SLL rl ro' ro' ro' ro' ro >> rl ro >> imm ro << rl ro << imm 45 46 47 48 Immediate logical ro' = ro SLL imm left shift AND Immediate AND OR Immediate OR Exclusive OR ro" = ro & ro' ro' = ro & imm ro" = ro | ro' ro' = ro | imm ro" = ro ^ ro' ro" ro' ro" ro' ro" ro & ro' ro & imm ro | ro' ro | imm ro ^ ro' 49 50 51 52 53 Status of overflow flag (OV) -: Not affected 1: Set to 1 when overflow occurs 138 User's Manual U13116EJ2V0UM00 APPENDIX B INSTRUCTION SETS Simultaneously Describable Flag Instruction Name Mnemonic Operation Trinomial Binomial Monomial Load/store Transfer Immediate Branch Loop Condition Group OV Page Immediate exclusive OR Binomial ro' = ro ^ imm ro' ro ^ imm 54 55 Less than ro" = LT (ro, ro') if (ro < ro') {ro" else {ro" 0x0000000001} 0x0000000000} Clear Increment Decrement CLR (ro) ro' = ro + 1 ro' = ro - 1 ro ro' ro' 0x0000000000 ro + 1 ro - 1 1 1 1 - ro} ro} 58 59 60 61 Absolute value ro' = ABS (ro) if (ro < 0) {ro' else {ro' One's complement ro' = ~ ro Two's complement ro' = - ro Clip ro' = CLIP (ro) ro' ro' ~ ro - ro 1 1 62 63 64 if (ro > 0x007FFFFFFF) {ro' 0x007FFFFFFF} else if (ro < 0xFF80000000) Monomial {ro' else {ro' Round ro' = ROUND (ro) 0xFF80000000} ro} 1 65 if (ro > 0x007FFF0000) {ro' 0x007FFF0000} else if (ro > 0xFF80000000) {ro' else {ro' 0xFF80000000} (ro + 0x8000) & 0xFFFFFF0000} Exponent ro' = EXP (ro) ro' ro' ro' ro' log 2 ro ro' + ro ro' - ro 1 1 1 ro 66 Put Accumulative add Accumulative subtract ro' = ro ro' + = ro ro' - = ro 68 69 70 Status of overflow flag (OV) -: Not affected 1: Set to 1 when overflow occurs User's Manual U13116EJ2V0UM00 139 APPENDIX B INSTRUCTION SETS Simultaneously Describable Flag Instruction Name Mnemonic Operation Trinomial Binomial Monomial Load/store Transfer Immediate Branch Loop Condition Group OV Page Divide Monomial ro'/ = ro if (sign (ro') = = sign (ro)) {ro' else {ro' (ro' + ro) << 1} (ro' - ro) << 1} 1 72 if (sign (ro') = = 0) {ro' Parallel load/store ro = *dpx_mod ro' = *dpy_mod ro = *dpx_mod *dpy_mod = rh *dpx_mod = rh ro = *dpy_mod *dpx_mod = rh *dpy_mod = rh' Load/store Section load/store dest = *dpx_mod dest' = *dpy_mod dest = *dpx_mod *dpy_mod = source *dpx_mod = source dest = *dpy_mod *dpx_mod = source *dpy_mod = source' Direct addressing load/store dest = *addr *addr = source dest dest' dest *dpy *dpx dest *dpx dpy dest *addr dest *dp dest rl *dpx, *dpy *dpx, source source, *dpy source, source' *addr source *dp source rl source 94 89 85 79 *dpx rh, *dpy rh' *dpx rh, ro *dpy ro *dpx, *dpy rh ro ro' + 1} *dpy 75 *dpx, ro' Immediate value dest = *dp_imm index load/store *dp_imm = source Transfer Inter-register transfer dest = rl rl = source Status of overflow flag (OV) -: Not affected 1: Set to 1 when overflow occurs 140 User's Manual U13116EJ2V0UM00 APPENDIX B INSTRUCTION SETS Simultaneously Describable Flag Instruction Name Mnemonic Operation Trinomial Binomial Monomial Load/store Transfer Immediate Branch Loop Condition Group Page OV Immediate value set Immediate set rl = imm (imm = 0-0xFFFF) dp = imm (imm = 0-0xFFFF) dn = imm (imm = 0-0xFFFF) dm = imm (imm = 1-0xFFFF) rl imm 97 dp imm dn imm dm imm Jump Register indirect jump JMP imm JMP dp PC PC imm dp 100 101 Subroutine call CALL imm SP STK PC SP + 1 PC + 1 imm SP + 1 PC + 1 dp STK SP - 1 STK SP - 1 102 Branch Register indirect subroutine call Return CALL dp SP STK PC 104 RET PC SP 105 Interrupt return RETI PC STK 106 Restores IE flag. Repeat Hardware loop REP count Start RC RF Repeat PC RC End PC RF Status of overflow flag (OV) -: Not affected 1: Set to 1 when overflow occurs count 0 PC RC - 1 PC + 1 1 108 User's Manual U13116EJ2V0UM00 141 APPENDIX B INSTRUCTION SETS Simultaneously Describable Flag Instruction Name Mnemonic Operation Trinomial Binomial Monomial Load/store Transfer Immediate Branch Loop Condition Group OV Page Loop LOOP count (For repeating instructions of 2 or more lines) Start RC RF count 0 PC RC - 1 PC + 1 1 110 Repeat PC RC End PC RF Hardware loop Loop pop LPOP LC LEA LSA LSP LSR3 LSR2 LSR1 LSP - 1 PC + 1 112 No operation NOP HALT STOP PC 115 116 117 118 119 Control Halt Stop CPU stops. CPU, PLL, OSC stop. Discards interrupt requests. Conditional judge Forget interrupt FINT Condition IF (ro cond) Status of overflow flag (OV) -: Not affected 1: Set to 1 when overflow occurs 142 Condition User's Manual U13116EJ2V0UM00 [MEMO] User's Manual U13116EJ2V0UM00 143 APPENDIX C INDEX [0] 1-bit shift multiply add .................................................. 32 16-bit shift multiply add ................................................ 34 One's complement ....................................................... 62 Two's complement ....................................................... 63 [A] Absolute value .............................................................. 61 Accumulate add ........................................................... 69 Accumulate subtract .................................................... 70 Add ................................................................................ 38 AND .............................................................................. 49 Arithmetic right shift ..................................................... 42 Immediate exclusive OR .............................................. 54 Immediate logical left shift ........................................... 48 Immediate logical right shift ......................................... 46 Immediate OR .............................................................. 52 Immediate sub .............................................................. 41 Immediate value index load/store ............................... 89 Immediate value set ..................................................... 97 Increment ...................................................................... 59 Inter-register transfer ................................................... 94 Interrupt return ........................................................... 106 [J] Jump ........................................................................... 100 [L] [C] Less than ...................................................................... 55 Clear ............................................................................. 58 Clip ................................................................................ 64 Condition .................................................................... 119 [D] [M] Decrement .................................................................... 60 Direct addressing load/store ........................................ 85 Divide ............................................................................ 72 [E] [N] Exclusive OR ................................................................ 53 Exponent ....................................................................... 66 [F] Forget interrupt ........................................................... 118 [H] Halt .............................................................................. 116 [I] [R] Immediate add .............................................................. 39 Immediate AND ............................................................ 50 Immediate arithmetic right shift ................................... 44 Register indirect jump ................................................ 101 Register indirect subroutine call ................................ 104 No operation ............................................................... 115 [O] OR ................................................................................. 51 [P] Parallel load/store ........................................................ 75 Put ................................................................................. 68 Multiply .......................................................................... 37 Multiply add .................................................................. 24 Multiply sub .................................................................. 26 Logical left shift ............................................................ 47 Logical right shift .......................................................... 45 Loop pop ..................................................................... 112 Loop ............................................................................ 110 144 User's Manual U13116EJ2V0UM00 APPENDIX C INDEX Repeat ........................................................................ 108 Return ......................................................................... 105 Round ........................................................................... 65 [S] Section load/store ........................................................ 79 Sign unsign multiply add ............................................. 28 Stop ............................................................................. 117 Sub ................................................................................ 40 Subroutine call ........................................................... 102 [U] Unsign unsign multiply add ......................................... 30 User's Manual U13116EJ2V0UM00 145 [MEMO] 146 User's Manual U13116EJ2V0UM00 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6465-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: 044-548-7900 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 99.1 Excellent Good Acceptable Poor |
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